MOS-AK Munich 2018

Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
Spring'18 MOS-AK Workshop
Munich, March 13, 2018

Calendar

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Books

Mission

Committee

MOS-AK: Enabling Compact Modeling R&D Exchange

Sponsor and Technical MOS-AK Program Promoters

Lead Sponsor

Publishing Partner

MOS-AK Workshop Program

Important Dates:

Call for Papers - Dec. 2017
2nd Announcement - Jan. 2018
Final Workshop Program - Feb. 2018
Compact Modeling Events - March 13-16, 2018

March 13: 2018 Q1 MOS-AK SPICE/Verilog-A Modeling Workshop
March 15-16: 2018 Q1 CMC Meeting (co-located)

Venue:

Infineon Technologies AG
Am Campeon 1-12
D-85579 Neubiberg
Building no. 3
Room: 03.1.158

Agenda

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Citation

Citation & Abstract

9:00-12:00

MOS-AK Morning Session

T_0

MOS-AK Workshop Opening
Klaus-Willi Pieper; Infineon Technologies AG, Neubiberg, (D)
Wladek Grabinski; MOS-AK (EU)

T_1

Overview of the Compact Modeling at Infineon
Klaus-Willi Pieper
Infineon Technologies AG, Neubiberg, (D);

T_2

Advanced Fast on-wafer Low-frequency Noise Measurement with High Resolution, Wide Bandwidth and Large Biasing Current Range
James Ma, Lianfeng Yang and Zhihong Liu
ProPlus Design Solutions Inc. (US)

Coffee Break

T_3

Advances in Statistical Compact Modeling
Dr. Volker Gloeckel* and Dr. Elmar Gondro**
*MunEDA; **Infineon Technologies

T_4

Compact Modeling of Nanomagnetic Logic Devices and Circuits
Markus Becherer, Simon Mendisch and Grazvydas Ziemys
Technische Universität München (D)

P_1

Devices for Nanomagnetic Logic
Gražvydas Žiemys
Technische Universität München (D)

T_5

Modelling Emerging Devices through EU ASCENT Network
Paul Roseingrave
Tyndall National Institute (IE)

12:00-13:00

Lunch Break

MOS-AK Panel: Compact Model Licensing
Peter Lee; CMC Chair

13:00-16:00

MOS-AK Afternoon Session

T_6

How Is CMC Standard Model Implemented and Verified In Simulator?
Jushan Xie
Cadence (US)

T_7

Virtual Prototyping for Power Diode and IGBT Development
Maria Cotorogea*, Peter Türkes*, Andreas Groove**
*Infineon Technologies AG, Neubiberg, (D); **Infineon Technologies AG, Warstein-Belecke (D)

Abstract:
Multidisciplinary virtual prototyping with respect to the switching behavior becomes more and more important for the efficient development of new semiconductor power devices and their packages. It enables the prediction of the performance of new device technologies or old technologies in new packages in an early design phase and helps reducing learning cycles by the use of virtual iterations during design optimization. The switching behavior of IGBT modules is determined on one hand by the switching conditions imposed by the outer circuit and the driver and on the other hand by the semiconductor devices themselves and the package they are mounted in. Chip, module and test circuit have inherent electrical and thermal parasitics. High current and voltage slopes during switching at short time scales and self-heating at larger time scales, requires the virtual prototyping approach to take them into account. It needs appropriate electro-thermal models for the IGBTs and the diodes, as well as for the parasitics. One of the main tasks is to identify and develop modeling techniques which can account for the 3D geometrical design using tools capable of facilitating a rapid iterative virtual design process. This challenge is addressed in the presented paper using model order reduction techniques to obtain equivalent electrical circuit models (compact models) implemented in the SPICE-like simulator SIMetrix. A prototype design flow incorporating these techniques is developed including interfaces between different simulation levels. Semiconductor device model calibration is also included, as well as post processing of predicted switching curves (several μs time scale over a wide range of switching conditions) to generate system-level models and enable the analysis of power device performance in application circuits (several ms time scale over a wide range of output powers, switching frequencies and cooling conditions). Transient current and voltage curves for single chip mounting in a buck-converter are used to assess simulation precision for calibrated models.

Coffee Break

T_8

Modeling of Device Aging - Example: Diode (Demo VA Files)
Franz Sischka*, Bertrand Ardouin**
*SisConsult (D), **XMOD Technologies (F)

T_9

Device Aging Simulations Enabling Circuit Cptimizations
Katja Puschkarsky
Infineon Technologies AG, Neubiberg, (D)

T_10

Integration of Aging Models Across Different EDA Environments
A case study implementing HCI and NBTI models for X-FAB XU035 CMOS technology
Fabio A. Velarde Gonzalez*, André Lange*, Sonja Crocoll**, Roland Jancke*
*Fraunhofer IIS/EAS (D), **X-FAB (D)

16:00

End of the MOS-AK Workshop

Extended MOS-AK/GSA Committee:

Committe

MOS-AK Technical Committee
MOS-AK/GSA North America
Chair: Pekka Ojala, Exar Corporation
Co-Chair: Geoffrey Coram, Analog Devices
Co-Chair: Prof. Jamal Deen, U.McMaster
Co-Chair: Roberto Tinti, Agilent EEsof Division
MOS-AK/GSA South America
Chair: Prof. Gilson I Wirth; UFRGS; Brazil
Co-Chair: Prof. Carlos Galup-Montoro, UFSC; Brazil
Co-Chair: Sergio Bampi, UFRGS, Brazil
Co-Chair: Antonio Cerdeira Altuzarra, Cinvestav - IPN, Mexico
MOS-AK/GSA Europe
Chair: Ehrenfried Seebacher, AMS, Austria
Co-Chair: Suba Subramaniam, XFab, XFab, Germany
Co-Chair: Prof. Benjamin Iniguez, URV, Spain
Co-Chair: Franz Sischka, SisConsult, Germany
MOS-AK/GSA Asia/South Pacific
Chair: Sadayuki Yoshitomi, Toshiba (J)
Co-Chair: Min Zhang, XMOD Technologies, (CN)
Co-Chair: Xing Zhou, NTU Singapore (SG)
Co-Chair: A.B. Bhattacharyya, JIIT New Delhi (IN)

No.#9309

update: Mar. 2018 (rev. F)