Abstract: 
MOS-AK is a HiTech forum to discuss the frontiers of electron device modeling with emphasis on simulation-aware compact/SPICE models and its Verilog-A standardization.

Abstract: 
Free and Open Source Software for Education (FOSSEE) is a project initiated by the Ministry of Education at IIT Bombay. It promotes many open source software systems, such as Scilab, Python, R, OpenModelica, OpenFOAM and DWSIM. By combining KiCAD and Ngspice, FOSSEE has developed an open source circuit simulation software eSim. By incorporating GHDL, eSim has been made capable of carrying out mixed signal simulation. This capability has been extended to simulate circuits with microcontrollers. Finally, the FOSSEE team is in the process of creating a cloud version of eSim. FOSSEE carries out several activities to promote circuit simulation through eSim. It has trained about 10,000 students and 5,000 teachers on the use of eSim. It helps colleges migrate their labs from proprietary software to eSim. More than 200 electronic circuits have been coded in eSim by students across India, and these are released as open educational resources. The FOSSEE team has also created automatic converters to migrate PSpice and LTSpice schematics to KiCAD, and hence, eSim. More than 100 such coverted circuits are released as open educational resource.

Abstract: 
In this talk, a series of memristor models is presented. The modeling methodology is mainly focused on developing memristor models that are useful for future circuit and system designers. Special attention is devoted to models for massive processing and IoT applications.

Abstract: 
As technology evolves, more and more functions and applications are readily implemented using CMOS circuitry, which makes them commonplace in our daily life. But ICs are not made of transistors only; many passive structures have to be built on the same chip to obtain the desired response of the circuit. Furthermore, the response of these structures cannot be limited to only a certain frequency band, as they will be present for the complete range of operation of the circuit. In this talk we present the models of an integrated inductor and that of a coplanar waveguide (CPW), compared to measurements up to 60 GHz. These are common structures now present in almost all modern ICs.

Abstract: 
The talk reports an analysis of the gate degradation induced by long-term forward gate stress in GaN-on-Si HEMTs with p-type gate, controlled by a Schottky metal/p-GaN junction. In particular, time-dependent gate breakdown is investigated as function of different geometries, gate process splits, and gate biases. The lateral removal (~ 120 nm) of gate metal (TiN) from the edges of the gate improves the device lifetime because it suppresses the onset of the leakage current flow occurring at the gate edges for relatively high gate voltage. Moreover, the adoption of devices with a different AlGaN barrier thickness and aluminum percentage (Al%), allowed us to identify the degradation of the AlGaN barrier as responsible for time-dependent gate breakdown at room temperature.

Abstract: 
The semiconductor device model is an essential element in circuit simulations that predict design performance, provide a framework for design centering and tolerancing, and aid in troubleshooting. Modern multi-objective optimization approaches in power electronics rely heavily on predictive device models. The presentation focuses on datasheet-driven compact modeling of SiC power MOSFET and GaN HEMT. The parameter set of these presented models can be extracted from the data commonly available in datasheets. Both the models incorporate extensive third quadrant behavior allowing accurate and efficient simulation of synchronous rectifications. Verilog-A and LTSpice implementation allow wider use of the models.

Abstract: 
Amorphous Oxide Semiconductors Thin Film Transistors, (AOSTFTs) are widely used in OLED displays controllers, due to their high mobility values. At the same time, other applications are under development, requiring specific models for these devices. Our group has been working on the development of DC and AC models to represent the I-V and C-V characteristics of bottom gate staggered structures. The new model for single gate AOSTFTs is described in Verilog-A, for using in SmartSPICE. It was validated for IGZO TFTs using simulations and experimental DC and AC measurements. For double-gate TFTs, the IV model was developed, described in Verilog-A and validated.

Abstract: 
The imperative need of increasing the battery life in mobile devices has motivated researchers to develop ultra-low voltage operation circuits. Therefore, the interest in the weak conduction of MOSFETs is rapidly growing. The drain current in weak conduction presents two exponential dependencies: one that is a function of the gate bias and another dependency that is a function of the drain bias. We review the following parameter extraction methods for weak- conduction: Transconductance-to-Current-Ratio (TCR), the integral functions H1 and H2, direct fitting, and the integral functions A and B. The methods were tested using measured data of polycrystalline silicon (poly-Si) thin-film transistors (TFTs). The two exponential coefficients were extracted and significant differences between them were found, which contradicts previously common assumptions. The methods based on numerical integration reduce the extraction uncertainties arising from the presence of noise in the measurements.