Abstract: 
In the last year, several important updates have been made to the Berkeley Model and Algorithm Prototyping Platform (MAPP), enhancing its device modelling capabilities. VAPP, the Berkeley Verilog-A Parser and Processor, now generates derivative code for device equations, speeding up model evaluation significantly. VAPP's backend has also been redesigned to not only handle valid implicit contributions in Verilog-A models, but also detect related problems in them. MAPP's multiphysics modules now support devices with thermal, magnetic, mechanical, spintronic, chemical (reaction rate) connections as well as the optical ones shown in the last year. Moreover, the ModSpec format in MAPP for specifying device models has enabled new table-based modelling techniques that can both generate compact models from tabulated measurement data and speed up existing device models. Last but not least, new device models, including those for ESD clamps and memristors, have been prototyped in MAPP. The process also demonstrates MAPP's usefulness in debugging and analyzing compact models.

Abstract: 
With rapid advancements of emerging devices, a data-oriented device modeling approach is in urgent need for early assessment of circuit applications. A universal SPICE modeling method with artificial neural network is presented. Several techniques to improve the model accuracy are proposed, from the data pre-processing to the network sizing. Applicability of the artificial neural network based modeling approach for circuit simulations will also be discussed. Finally it is concluded that the neural network architecture can serve as a universal SPICE model.

Abstract: 
For model developers that endeavor to maintain consistencies of linear and nonlinear models’ performance among different simulators, it can be problematic as different simulator vendors have their own implementations of the components used in models’ development. These differences cause variations in the models’ behavior, which can be significant and sometimes unacceptable. This situation can be alleviated to great extent through the usage of Verilog-A coded models. When using the Verilog-A models in different simulators, compatability would seem automatic due to the use of a unified code-base. However, it is up to the simulator vendors to provide consistent interpretation of the code to provide the consistency desired. In practice today the authors find that the interpreters treat the same Verilog-A code-base slightly differently. First of all, not all the system APIs are supported; secondly, interpreters may have different requirements on how the nodes or branches are coded and there may be other glitches or differences. In this paper, we highlight the inter-operation of a typical nonlinear GaN transistor model in four simulators, including Keysight’s ADS and Genesys, AWR’s Microwave Office, and Cadence Spectre. Other model examples may be shown, time permitting.

Abstract: 
This paper presents a new generation reliability model, specifically for FinFET and advanced CMOS technologies. FinFET and advanced CMOS show some new phenomena that no existing reliability model seems to model them accurately. The new generation in this presentation can fit it very well. Most existing EDA reliability models either ignores or have inaccurate BTI recovery effect, new methodology is developed for BTI recovery effect prediction and circuit simulation. This model is validated for full stress/recovery range in the FinFET technology. Other important features, such as the history effect and frequency dependence are included in this new reliability model. This new generation reliability model is implemented into Cadence reliability tools, an extraction tool is developed for Spice model extraction.