Arbeitskreis MOS-Modelle und Parameterextraktion MOS Modeling and Parameter Extraction Working Group MOS-AK/GSA ESSDERC/ESSCIRC Workshop Sept.17, 2010  Seville

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Poster Session

Venue:	Barceló Renacimiento Hotel Seville
Agenda:	Sept. 17, 2010 MOS-AK/GSA ESSDERC/ESSCIRC Workshop "Frontiers of the Compact Modeling for Advanced Analog/RF Applications"
Display Format: Citation Citation & Abstract
11:30-12:00	Poster Session - Chair: W.Grabinski
P_1	Characterization of wearout mechanisms in MOSFET Raúl Fernández and Ignacio Gil Universitat Politècnica de Catalunya (ES) Abstract:  This work addresses the impact of wearout mechanisms on the overall behavior of MOSFETs. Particularly, the effect of time-dependent dielectric breakdown (TDDB) and negative bias temperature instability (NBTI) have been analyzed. In order to perform these experiments, the samples have been subjected to different voltage and temperature stress, respectively. The results show a reduction of the saturation drain current in the samples under TDDB stress. Moreover, a gate-drain and/or gate-source current flows when the dielectric breakdown appears. The value of this current depends on the breakdown hardness. However, in most of the cases the transistors don’t lose their functionality. Regarding NBTI, the experimental shows that voltage threshold is increased. Specifically, a power law dependence of the voltage threshold against the stress time is observed. Furthermore, the static and dynamic NBTI stress has been compared showing that the voltage threshold shift in AC is almost a half of the DC case. The presented characterization is useful in order to develop new compact MOSFET models which take into account the wearout mechanisms and to evaluate the impact of them on circuit functionality.
P_2	Extraction of Low Frequency Noise and Transistor Mismatch Parameters at Cryogenic Temperature for Design of CMOS Imagers in a 0.18 µm Mixed Analog-Digital Process Anne-Sophie Royet, Patrick Martin and Fabrice Guellec CEA, LETI, MINATEC, Grenoble (F) Abstract:  This paper presents experimental results on low frequency noise and mismatch in different 1.8 V and 3.3 V MOS transistors of a 0.18 µm mixed analog-digital CMOS process at room temperature and at cryogenic temperature (T < 200 K). We show that there is a similar behavior between the two fluctuations phenomena, low frequency noise and transistor matching, although the first one is related to fluctuations during the trapping-detrapping of carriers near the SiO2/Si interface and the second one to fluctuations in the number of dopants. The mismatch parameters ABETA and AGAMMA of the Pelgrom’s model systematically increase at low temperature. The threshold voltage mismatch parameter AVT0 generally increases at low temperature as expected from the enlargement of the depletion layer and consequently a higher number of dopants. These noise and mismatch results have strong implications for design of cooled CMOS imagers.
P_3	New threshold voltage model for symmetrical undoped DGMOSFET Pawel Salek, Lidia Lukasiak, Andrzej Jakubowski Institute of Microelectronics and Optoelectronics, WUT (PL) Abstract:  Double-gate (DG) structure improves SCE control. Additionally, in undoped DG devices the problem of the fluctuations of impurity concentration is greatly reduced. The standard threshold definition is no longer valid in undoped devices, therefore a new threshold voltage model is proposed for symmetrical undoped double gate MOS transistor (DGMOSFET). It is assumed that the threshold condition is fulfilled when the deviation of the dependence of surface potential on gate voltage is sufficiently large. To obtain a closed-form description of threshold voltage, an analytical approximation of the surface potential – gate voltage dependence was required (quantum effects not taken into account). Therefore, a parabolic approximation of the potential distribution across the channel was derived using Lambert’s W-function. A comparison of the threshold voltage calculated according to the new model with that extracted from ATLAS simulations of I-V characteristics for a wide range of device parameters (channel and oxide thickness) indicated that the best fit is obtained when sufficiently large deviation mentioned above is 1.1 kT/q. Relative error does not exceed 10 percent over the entire range of channel and dielectric thickness interesting for modern microelectronics. The model takes into account the dependence of the threshold voltage on the transistor dimensions.
P_4	BPV method as a tool for statistical compact modeling of SOI CMOS technology Marat Yakupov*, Daniel Tomaszewski*, Krzysztof Kucharski*, Wladek Grabinski** *ITE (PL), **GMC (CH) Abstract:  A statistical compact modeling methodology based on backward propagation of variance (BPV) method has been presented. It has been used for development of statistical models characterizing global variations of a standard bulk CMOS and of a fully depleted (FD) SOI CMOS technologies used in ITE. The statistical models have been derived for the LEVEL=3 and EKV MOSFET models. In both cases I-V data as well as threshold voltages, transconductances and output conductances of series of different size MOS devices have been used as process control monitor (PCM) data. Statistical distributions of the PCM data have been used to evaluate standard deviations of several so-called process parameters responsible for process variability: flat-band voltage VFB, substrate doping concentration NSUB, gate dielectric thickness TOX, low-field mobility UO, channel widening/narrowing DW, and channel shortening DL. Based on the derived statistical compact models a Monte-Carlo (MC) analysis of simple digital and analog CMOS blocks has been done. The presented methodology is being developed now towards statistical modeling of multi-gate MOSFETs.
P_5	Interface AlGaN/GaN HEMT Study at Room Temperature Lemia Semra*, Azzedine Telia*, Ali Soltani** *LMI, UMC (Dz),**IEMN, UMR-CNRS (F) Abstract:  High Electron Mobility Transistors (HEMT) are very useful in microwave power applications, especially in wireless communications. In this work an Al0.25Ga0.75N/GaN heterostructure is studied. An analysis of frequency dispersion in capacitance and conductance of gate-source contact of AlGaN/GaN HEMT was performed. Capacitance and conductance were measured varying bias voltage at room temperature. In order to characterize trap states the conductance method. Hence, the parallel conductance Gp and capacitance Cp were calculated, and consequently interface trap density Dit and time constant  are deduced. The analysis is performed assuming a continuum of levels yielding to a trap density of approximately 10+12 cm-2eV-1 and a time constant about µs. Variations versus frequency of calculated conductance using different Cit and Rit deduced from the conductance method correspond to the experimental one until a certain value of frequency beyond witch divergence is noticed. In addition, calculated capacitance variations showed deviation from experimental data. These results stipulate that traps are not only located at the interface.
P_6	Improved RPI TFT compact model: extrinsic and with correct account of positive differential conductance after saturation Valentin Turin*, Gennady Zebrev**, Benjamin Iñiguez***, and Michael Shur**** *Orel STU, **MEPHI, ***URV, ****RPI Abstract:  The RPI TFT and MOSFET Level 1 models, based on the simplest quadratic Shockley's MOSFET model, are used, for example, in AIM-Spice, Cadence PSPICE, Synopsys HSPICE, and Silvaco SmartSpice circuit simulators. These models use channel-length modulation parameter λ to account for non-zero differential conductance after saturation due to Channel Length Modulation (CLM), Drain Induced Barrier Lowering (DIBL), and self-heating (SH) effects. This is done by multiplying the expression for the drain current by the 1+λVDS factor, where VDS is the drain-to-source bias. However, this traditional approach suffers from non-monotonic behavior of the differential conductance with increasing drain-to-source bias. For example, we found that if the differential conductance after saturation equals 25% or 50% of its value in the linear regime, the maximum differential conductance reaches 108% or 124% of its value in the linear regime, respectively. However, to be useful in analog circuit simulations, the compact model should accurately reproduce the output conductance. To overcome this disadvantage of traditional models, we offered a new approach that gives the correct monotonic decrease of the differential conductance. This new approach can be applied also to BSIM3 and BSIM4 models to account for non-zero differential conductance after saturation. In addition, we have generalized the improved model into the extrinsic compact model that accounts for the source and drain series resistances analytically. The extrinsic compact model improves convergence and speed of compact modeling and has advantages for the computer-aided design of integrated circuits.
P_7	Techniques for accurate flicker noise measurement up to 40 MHz Toe Naing Swe Cascade Microtech, Inc. Abstract:  With the advancement of semiconductor devices and their applications, needs for accurate, repeatable and reliable flicker noise data has becoming more and more desirable for accurate device characterization, as well as process development. This paper describes how to achieve high-precision on-wafer flicker noise measurement up to frequency as high as 40 MHz. The techniques required to ensure reliable on-wafer flicker noise characterization, such as preventing external noise influence on the measurement set up, as well as minimizing system residual capacitance to achieve higher frequency bandwidth, are discussed. The measurement results of various types of devices are also presented.
P_8	Combining Process and Statistical Variability in the Evaluation of the Effectiveness of Corners in Digital Circuit Parametric Yield Analysis P. Asenov, N. A. Kamsani, D. Reid, C. Millar, S. Roy, A. Asenov University of Glasgow Abstract:  This paper focuses on two main types of MOSFET variability – systematic (process) and statistical (random) variability and discusses the use of process corners as a measure of yield and circuit performance. We provide a methodology for performing large-scale statistical SPICE simulations as a means of evaluating the accuracy of corners in a system dominated by statistical variability and then expand the methodology to include both systematic and statistical variability within the same large-scale SPICE simulations. This large-scale statistical/systematic approach is compared to the “global + local” statistical corner approach, which consists of statistical simulations around the process corners. Finally 2D kernel density estimates are used to extract yield data from the statistical simulations to allow energy/delay/yield optimization to be performed. This in turn highlights the deficiencies of the statistical corner approach.
P_9	Free software tools in electronic design: a search and a preliminary selection C. Medrano, I. Plaza, M. Castro, F. Garcia-Sevilla, J.D. Martinez-Calero, Josep Pou Felix, M. Corbalan EUPT, UNED, EUETIT Abstract:  In this paper, we review electronic design free software tools. We have searched open source programs that help with several tasks of the electronic design flow: analog and digital simulation, schematic capture, printed circuit board design and hardware description language compilation and simulation. We have selected some of them which are worth working with using some rapid criteria. The criteria concern the following aspects: installation, information and documentation about the program, ability to work with simple examples and expectation of being maintained and improved in the future. Seventy four programs were rejected after this rapid test, and we picked twenty five for further research, being at least three or more programs for each of the tasks considered. We have performed an analysis of rejections and a summary of selected programs. The long term goal of the present work is to evaluate free software in electronic design, assessing the situation of these tools and selecting some of them for education or professional use.
P_10	A Verilog-A implementation of a model for spin-valve based current sensors A. Roldán*, C. Reig**, M.D. Cubells-Beltrán**, J.B. Roldán*, D. Ramírez**, S. Cardoso***, P.P. Freitas*** *Universidad de Granada (Spain), **Universitat de València (Spain), ***Instituto de Engenharia de Sistemas e Computadores - Microsistemas e Nanotecnologias (Portugal) Abstract:  In this work we propose a DC electrical model for spin-valve based GMR(Giant-Magnetoresistance) current sensors. The model has been developed making use of experimental results. It has been implemented in Verilog-A and used in simulations of characteristic instrumentation circuits.
P_11	Recent Developments on the EPFL-High Voltage MOSFET Model (EPFL-HVMOS) Antonios Bazigos*, François Krummenacher*, Jean-Michel Sallèse* *EPFL Abstract:  We present the latest developments and some preliminary results on High-Voltage MOSFET modelling at EPFL. A novel physics-based compact model is derived for the drift region. It includes velocity saturation and Poisson equation in a self consistent formalism. Next, this drift extension has been combined with a non-uniformly doped MOSFET compact model for the low voltage section of the device. The complete model has been implemented in Verilog-A language. Evaluation against TCAD simulations and actual measurements on state-of-art HV-MOS devices confirm the soundness of this approach.
P_12	Bipolar Transistor Modeling: Present and Future Trend Anjan Chakravorty and Surajit Sen Meridian Software Technology (P) Ltd, India Abstract:  Aggressively downscaled HBT technologies and stringent design specification of RF-analog circuits compelled the bipolar transistor modeling community to face multifarious challenges. This resulted into complicated model equations as well as equivalent circuits unlike those of SPICE Gummel-Poon model. Such sophisticated bipolar transistor models (VBIC and HICUM/L2) are supposed to allow the use of newer technology as well as to meet the design specifications of modern circuits. However, a safer use of such models heavily depends on the accuracy of model parameter extraction. Here, we present the inaccuracy of such models under certain operating conditions along with possible improvements and some issues on parameter extractions. Few representative model equations and results showcase the suggested modeling improvements and accuracy of extracted parameters. Also a pointer is given indicating the development of smarter parameter extraction modules which may be relevant for design houses.
P_13	Analytical two-dimensional model for the parasitic source/drain resistance in DG-MOSFETs Thomas Holtji*, Mike Schwarz* ** and Alexander Kloes* *University of Applied Sciences Giessen (GER), **Universitat Rovira i Virgili (ESP) Abstract:  We present a new way to calculate the parasitic source/drain resistances in DG-MOSFETs. The two-dimensional model in analytical closed form is derived by using the conformal mapping technique and describes accurately the influence of source/drain geometries on the access resistance. The approach introduces only two fitting parameters for a bias dependent mobility model, where these parameters can be kept constant for a given geometry of the source/drain extension areas. It is able to predict the parasitic source/drain resistances for various devices like DG-MOSFETs, DG-MOSFETs with RSD and DG-MOSFETs with RSD and wrapped contacts. The model is compared with data simulated by TCAD Sentaurus for channel length down to 20nm and is in good agreement to these numerical results. The model is a good starting point to predict the values of parasitic source/drain resistances and in this way can contribute to the definition of a new compact model for future DG-MOSFET devices having very short channel lengths.
P_14	Hybrid CMOS-MEMS/NEMS technologies at IMB-CNM Emilio Lora-Tamayo, Joan Bausells and Francesc Pérez-Murano IMB-CNM (ESP) Abstract:  This poster presents the technological capabilities of the Barcelona Microelectronics Institute (IMB) of the National Microelectronics Center (CNM). Its integrated micro and nanofabrication clean room is a large scale facility which supports the research of IMB-CNM and has open access for external users. We highlight the research results and capabilities in the integration of CMOS with MEMS/NEMS devices, and in particular with NEMS resonators.
P_15	Analytical Modelling of Short Channel Planar FDSOI and Triple-gateFET Transistors R. Ritzenthaler*, F. Lime*, O. Faynot**, S. Cristoloveanu***, and B. Iñiguez* *Universitat Rovira I Virgili (ESP) **CEA-LETI Grenoble (F) ***IMEP-LAHC, Minatec Grenoble (F) Abstract:  In this work, a short channel model is developed in order to obtain analytical expressions of the static characteristics of Triple-gateFETs (TGFETs)/Planar FDSOI transistors. First, a core model is developed in order to get the expressions of the subthreshold characteristics of advanced Pi-gateFET transistors (adaptable to TGFETs/FinFETs/DGFETs/Planar FDSOI transistors). Based on the solution of the 3D Laplace’s equation, the interface coupling in the structure is accurately described. The short-channel characteristics (subthreshold current, subthreshold Slope, Roll-off and DIBL) are calculated and compared to experimental data with an excellent agreement, without the need of any fitting parameters. Additionally, it is shown that the proposed analytical equation for the 3D potential distribution can be used to determine the scalability of a wide range of Multiple-gate FET transistors. A pseudo-compact subthreshold slope formula is also proposed in the case of TGFETs in order to provide a simplified scaling expression. Then, for TGFETs and planar FDSOI devices, it is shown that the model can be extended to the other regimes using simplified expressions (strong inversion) and interpolation functions (between weak and strong inversion regimes) in order to get the complete static characteristics.
12:00	End of the Poster Session
Committees:	Local Organizing Committee: Andres Godoy, UGR Benjamin Inigues, URV Rodrigo Picos, UIB Extended MOS-AK/GSA Committee: Lisa Tafoya, Vice President, Global Semiconductor Alliance (GSA) Chelsea Boone GSA; Senior Research Analyst Wladek Grabinski, GMC Suisse; MOS-AK/GSA Group Manager MOS-AK/GSA North America: Chair: Pekka Ojala, Exar Corporation Co-Chair: Geoffrey Coram, Analog Devices Co-Chair: Prof. Jamal Deen, U.McMaster MOS-AK/GSA South America: Chair: Prof. Gilson I Wirth; UFRGS; Brazil Co-Chair: Prof. Carlos Galup-Montor, UFSC; Brazil MOS-AK/GSA Europe: Chair: Ehrenfried Seebacher, austriamicrosystems AG Co-Chair: Sebastian Schmidt, XFab Co-Chair: Prof. Benjamin Iniguez, URV MOS-AK/GSA Asia/Pacific: Chair: Goichi Yokomizo, STARC, Japan Co-Chair: Sadayuki Yoshitomi, Toshiba, Japan Co-Chair: Xing Zhou, NTU, Singapore

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update: Sept. 2010 (rev. F)

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