Embassy of Switzerland
2900 Cathedral Ave, NW, 
Washington, DC 20008
USA

Abstract: 
Formed in 1996 as a collaboration of foundries, fabless companies, IDMs and EDA vendors, the Compact Model Council has standardized numerous SPICE models for silicon integrated circuit technologies. This presentation will provide an overview of the CMC’s standards, operations and membership benefits. Current projects funded at universities and new standards on the horizon will also be described. Finally, the CMC’s acquisition by the Silicon Integration Initiative (Si2) partners it with the world’s leading EDA standards organization. This change poises the CMC, now known as the Compact Model Coalition, to have an even greater impact on the semiconductor industry. These expectations will be discussed.

Abstract: 
TiN films with poly-Si-n+ cap layer have been used as metal gate electrode in MOS capacitors. Poly-Si n+/TiN stack layers were obtained by Ti e-beam evaporation, with additional electron cyclotron resonance (ECR) plasma nitridation, on SiO2(10nm)/Si substrates. On the TiN/SiO2/Si structures were deposited a-Si films using in the same ECR system. After phosphorus ion implantation and rapid thermal annealing were carried out, to get the poly-Si-n+ cap layers. Eight different poly-Si n+/TiN/ SiO2/Si structures were used to fabricate MOS capacitors. The formation of poly-Si n+/TiN stack layers were confirmed by SEM and EDS, indicating that the Ti and N incorporation in uniform and conformal TiN layers, with thickness values lower than 10 nm. Furthermore, poly-Si-n+ cap layers on TiN films can be presented high efficiency to keep the TiN thermal stability. Physical characteristics, such as uniform and conformal films, which present thermal stability, are mandatory for sub-22 nm CMOS technology. Capacitance-Voltage curves of MOS capacitors were performed at 1 MHz, and no distortions occurred, indicating that our poly-Si n+/TiN/ SiO2/Si structure, which uses ECR system to get the films, is a new alternative to replace TiN structures, which have been used and obtained by Atomic Layer Deposition (ALD).

Abstract: 
A simulation framework (available in a software package) relying on a comprehensive physical model of charge transport and degradation phenomena in dielectric stacks is presented. This simulation suite allows reproducing the electrical measurements typically considered for the dielectric layer characterization (I-V, C-V, BTI VT shift, Charge-Pumping, SILC, gate and drain noise, stress) and reliability/variability prediction. The physical mechanisms governing charge-transport and degradation are modeled using a novel material-related microscopic approach that accounts in a self-consistent fashion for the charge transport (dominated by defect-assisted contributions), the associated power dissipation and temperature increase, the defect generation, and ion and vacancy diffusion and recombination. The physical properties of defects, which affects significantly the electrical behavior of the dielectric stacks, are derived from their atomistic configurations. This simulation package allows interpreting electrical characterization measurements (e.g. I-V, C-V, CP, VT increase/recovery during BTI, gate/drain current noise). Calibration on different technology is easy thanks to a dedicated automatic fitting module under development. Simulation results performed on a wide range of dielectric material demonstrate that the physical model adopted, which relies on the defect-driven charge transport and degradation, is the correct description for simulating electrical behavior of dielectric stacks in static and transient (under stress) conditions.

Abstract: 
The characterization and modeling of MOSFETs in the millimeter-wave region is a challenging task. The big problem is the stability of measurement data, which are very sensitive to the probing condition and surrounding environment. This leads to have occasional hardware calibration, which makes measurement itself much longer. Because this approach has not been feasible, it was not possible to see how the distributions of MOSFETs at the 60GHz are. We installed a 60GHz semi-auto measurement system and succeeded auto measurements using 12 inch wafers fabricated in TOSHIBA’s 65nm CMOS technologies. Investigation of statistical distribution (such as fT, fMAX etc.) have shown strong frequency dependence, which indicates the necessity of frequency formulation of such distributions. We studied statistical modeling using characteristic data of MOSFETs. By the introduction of intermediate variables and formulated correlations of model parameters, we succeeded to predict accurate correlation of fT, fMAX, parasitic resistances and capacitances.