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| M. Berroth, Uni
Stuttgart Design and Modeling Activities at INT, Uni Stuttgart |
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| J.
Rhayem, AMIS Belgium General Overview of Modeling and Test Methodology of HV MOSFET The presentation will cover DC and AC modeling aspect of High Voltage MOSFET. This part will show a solution to the limitation of standard model existing in software package to take into account some special effect of high voltage MOSFEST. A new methodology to generate realistic corners will also be briefly presented |
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| J. Haase,
IIS/ESA Fraunhofer Dresden Handling of Device Models in VHDL-AMS VHDL-AMS
is a
hardware description language that provides capabilities for describing
analog and mixed-signal systems on different levels of abstraction. The
language definition is an IEEE standard. The contribution will give a
proposal how typical tasks like model and parameter declaration and
initialization can be handled in VHDL-AMS. Problems in regard to the
interaction with simulator algorithms and variables will be discussed
for Spice-like device models. |
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| F.
Prégaldiny, PHASE/CNRS Strasbourg Fourth Generation MOSFET Model and its VHDL-AMS Implementation An overview of key concepts used to include the quantum mechanical effects (QME) in a fourth generation MOSFET model is presented. While the last decade has been dominated by Berkeley's BSIM3 and BSIM4 models (third generation models), a new type of compact models like HiSIM, SP or MM11 is more and more accepted in the semiconductor industry. These latter are all surface-potential-based models and, as a result, should be regarded as the fourth generation of MOSFET models. Based on the core of the MM11 model, we have developed new concepts to compute the exact value of the surface potential, i.e. accounting for the quantum effects. The model covers all operating regions from accumulation to inversion and is valid for all bias conditions. The moderate inversion region is particularly well described, as well as both linear and saturation regions. Our modeling of charges/transcapacitances and drain current shows an excellent behavior in terms of accuracy and speed, while requiring no additional parameters in comparison to a classical model (w/o QME). Finally, the VHDL-AMS implementation of the model is demonstrated and a representative set of simulation results is presented. Comparison with experimental data from different deep-submicron technologies is also provided. |
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| M.
Bucher, TUC; A. Bazigos, NTUA; F. Krummenacher*,
W. Grabinski*, *EPFL Exploring the 'Light Edition' of the EKV3.0 MOSFET Model The growing complexity of compact MOSFET models with an ever increasing number of parameters -- a recent model release has reached as much as 700(!) -- makes learning of MOSFET physics difficult for young scientists. In an attempt to reverse this trend and to present a concise, truly compact model, the EKV3.0 LE ("light edition") has been formulated. This model version retains the essential developments in EKV3.0, while sacrificing others, to the benefit of a reduced set of equations and parameters, as well as increased efficiency. In this paper, EKV3.0 LE is presented, and the essential effects contained in the model are explored and illustrated. The EKV3.0 LE is more amenable to analog design which does not always use the latest and most advanced CMOS technology. The simpler structure and reduced number of parameters clarifies the MOSFET physics and also simplifies parameter extraction procedures in many situations. |
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| T.
Gneiting, AdMOS MOS Parameter Extraction Based on a Standardized Set of Measured Data As CMOS
technology is scaling towards the nanometer regime, a new generation of
appropriate MOS simulation models is available for the design
community. While the last decade has been dominated by Berkeley's BSIM3
and BSIM4 models, new concepts like the HiSIM1 or the Philips MM11
model are accepted more and more in the semiconductor industry.
This poster presents a parameter extraction framework which can
generate those different model types from one unified set of measured
data. All important steps starting from the definition of the test
patterns through measurement, data handling, parameter extraction and
quality assurance are discussed. |
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| A. Lord, Cascade
Microtech Europe Optimizing on-wafer measurement performance for device characterization and modeling The fundamentals of DC and RF on-wafer measurements for device characterization are presented. High performance RF/DC test cells incorporating the latest instrumentation, probes and software are introduced with the implications for measurement and modeling clearly described. Calibration methods are reviewed and problem areas identified, with solutions. Finally, a new methodology for management of the test cell to optimize productivity and the modeling software performance is introduced. |
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| M. Tolikas, S. Mertens, Ansoft Nexxim: The Next State of the Art in Circuit Simulation This
presentation is an introduction to
Ansoft's new circuit simulation tool, Nexxim(TM). Nexxim(TM) provides
transient and harmonic-balance circuit simulation, with
transistor-level detail and SPICE-level accuracy. It offers unmatched
capacity and speed gains to handle the high nonlinearities and large
device counts characteristic of today's designs. An overview of the
software's capabilities will be presented, together with simulation
results and examples from the analog/mixed signal and signal integrity
markets. |
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F. Sischka: - new Agilent DC Analyzer E2070A driver - new Agilent PNA network analyzers driver (PNA series) - new graphics - new optimizers - new PlotOptimizer feature for easier curve fitting (demo of prototype) - improved interface to Spectre, new Spectre parser - BSIM-SOI toolkit A demo of IC-CAP 2003 will be available during the workshop meeting. |
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| I.
Kallfass*, H. Schumacher*, T. J. Brazil**, *Uni Ulm, **University
College Dublin Modelling of Frequency Dispersion Effects in Hetero Field Effect Transistors We present
a new approach to the accurate modelling of frequency dispersion
effects encountered in state-of-the-Art Hetero FETs. The empirical,
equivalent-circuit based model allows for the inclusion of individual
dispersion effects like selfheating, traps/surface states and impact
ionisation, taking into account the different time constants associated
with individual dispersion effects. The proposed technique allows for
accurate small- and large-signal modelling of frequency dispersion in
drain current characteristics in both the time- and frequency domain.
Verification of the model is carried out using pulsed-IV- as well as
moderate- to high-frequency S-parameter characterisation of a 0:15um
AlGaAs/GaAs pHEMT with an ft of 100GHz. Also, the modelling technique
is shown to be applicable to HFETs based on InP- and relaxed-SiGe
buffer substrates. |
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| M. Jutzi,
E. Gaugler, J. Kaiser, K. Eve, M. Berroth, Uni Stuttgart CMOS photodiodes Photodetectors fabricated in unmodified, commercially available CMOS-processes are reported. The 1/e- penetration depth of 850 nm light in Si is much larger than the thickness of the active regions in CMOS-technologies. Thus, slow diffusion photocurrents limit the photodetector bandwidth. Three detector concepts are compared. The first photodetector type makes use of the n+pp+-diode formed by n+ doped fingers, a lightly p-doped substrate and p+ doped fingers. A high reverse bias voltage of 40 V is necessary to achieve a 3-dB-bandwidth of 1.2 GHz. The second type of photodetector is screened from slow diffusion currents by an additional n-well to substrate diode. However, the photoresponsivity to 850 nm light is only 5 mA/W at -2 V. The third type relies on the concept of spatial modulation of the illumination pattern and comprises an illuminated and a shaded n-well to p-substrate photodiode. In the differential output slow diffusion photocurrents generated deep in the substrate are partly cancelled. S-parameter measurements indicate a 3 dB-bandwidth of 1.1 GHz at a small reverse bias voltage of 2 V and a photoresponsivity of 20 mA/W to 850 nm light. |
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| V.
Vassilev, IMEC MOSFET Breakdown and Snapback Modelling for ESD Protection Design in the State of the Art CMOS The
development of circuit and device Electrostatic Discharge (ESD)
reliability simulation tools is one of the critical challenges for
implementing the ITRS. This talk will present an approach for compact
modelling of the ESD stress domain (I~[A], time ~ [ns]) breakdown
and
snapback behaviour of the state of the art MOSFET structures for
the
need of pre-silicon ESD protection circuit optimisation. The impact of
the technology downscaling on the device characteristics will be
discussed, including the increased breakdown regime tunnelling currents
and electric fields. Equivalent circuit model will be presented
together with its implementation in SPECTRE, using SPECTRE AHDL. The
model parameter extraction methodology will be outlined as well,
including implementation in IC-CAP. Application examples for using the
snapback MOSFET models for optimisation of the ESD protection behaviour
of digital I/O cells will be presented and discussed at the end. |
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| E.
Seebacher, AMS CODESTAR: Compact Modeling of On-chip Passive Structures at High Frequencies The major goal of the European IST project CODESTAR (Compact modeling of on-chip passive structures at high frequencies) is to accelerate the design of passive on-chip structures like inductors, capacitors and critical parts of the interconnect layout. The target of the project is that the CODESTAR code reads the geometrical and physical information of the design problem taking into account the material properties of the design. The software solves the equations for the electromagnetic fields and the charge transport in the structure of the design. CODESTAR converts the result into an equivalent netlist that is submitted to order-reduction techniques to obtain an equivalent netlist of lower complexity valid in prescribed frequency ranges. An overview of the project and the status of the different work-packages will be discussed and especially the work-package WP4 will be presented in detail. The objective of the work package WP4 in the CODESTAR project is to design, fabricate and characterize test structures for RF passive devices and interconnects that will be used to benchmark both commercial tools and newly developed CODESTAR programs for TCAD simulation and compact model extraction. The selected RF test structures can be divided into 2 categories: standard structures (passive devices, RF interconnect structures) and challenging structures (guard rings, RF pads, LC cells). The selection and implementation of the test structures with respect to the inputs of the industrial partners is described as well as the used RF measurement techniques. |
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| M. Grözing, Uni
Stuttgart Close-in Phase Noise Issues in CMOS Oscillators Close-in phase noise of single-ended CMOS inverter ring oscillators is investigated theoretically and by measurements. The phase noise figure-of-merit is found to be dependent on the MOSFETs’ channel length, the oscillator stage number, the NMOS and PMOS flicker noise coefficients and the peak currents that discharge and charge the node capacitances. Design implications regarding stage number, gate length and the ratio of NMOS and PMOS gate widths are derived and verified by measurements. Further, the dependency of close-in phase noise on either current or voltage impression to the oscillator core is investigated. Current impression is found to decrease the phase noise compared to voltage impression. |
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