Abstract: 
As integrated circuit process technology nodes evolve to support higher density digital IC content so too must the methods used to simulate such circuits. Unfortunately simulating digital circuit behavior in Spice is difficult and computationally inefficient. These circuitries however can be effectively modeled in HDL languages such as VHDL, Verilog, SystemC etc. Hardware Description Languages such as VHDL-AMS, Verilog-AMS, SystemC-AMS are effective extensions that can be integrated into Spice simulators to address digital simulation, however mixed signal, analog elements used in ADC, DACs, Power management ICs, Jitter Attenuators and the like must be optimized and made compatible with HDL. Fortunately, many of the constructs necessary for mixed signal simulation with HDL have been previously advanced in Spice. In this presentation we will describe the method through which real world, mixed signal devices such those mentioned above can be efficiently modeled in TINA and our online version TINACloud multicore circuit simulators using mixed Spice-HDL model constructs.

Abstract: 
We will give an overview of several open-source tools that are useful for compact model parameter extraction. In particular, we will present our own tool, VerilogAE, which is a novel compiler solution for compact model parameter extraction.