Arbeitskreis Modellierung von Systemen und Parameterextraktion  Modeling of Systems and Parameter Extraction Working Group 12th International MOS-AK Workshop Silicon Valley, December 11, 2019

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MOS-AK Workshop Program

Important Dates:	Call for Papers - Oct. 2019 2nd Announcement - Nov. 2019 Final Workshop Program - Dec.2 2019 MOS-AK Workshop: 9:00 - 16:00 on Dec.11, 2019 in timefrme of IEDM and Q4 CMC Meetings
Venue:	Silvaco HQ 2811 Mission College Blvd., 6th Floor Santa Clara, California  95054
Agenda	Display Format: Citation Citation & Abstract
9:00-12:00	MOS-AK Morning Session Chair: Roberto S. Murphy, INAOE, Puebla (MX) and Bogdan Tudor, Silvaco (USA)
[0]	Welcome: MOS-AK Intoduction and IEEE EDS DL Update Bogdan Tudor and W. Grabinski Silvaco (USA) and MOS-AK (EU) Abstract:  MOS-AK Meetings are organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/Spice modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development, implementation, deployment and standardization within the main theme - frontiers of the compact modeling for nm-scale MEMS/NEMS designs, CMOS/SOI and HEMT IC simulation.
[1]	Si2 Compact Model Coalition: 2019 Update Peter M. Lee Si2 CMC (USA) Abstract:  This talk will summarize the accomplishments and ongoing initiatives of the Si2 Compact Model Coalition for 2019. The release of new standards, new releases of existing standards, look-ahead projects, and revised policies will be presented.
[2]	What's in the Standard? Establishing the CMC Policy for Verilog-A Models Geoffrey Coram Analog Devices, Inc. (USA) Abstract:  The Compact Model Coalition, part of the Silicon Integration Initiative (Si2), is developing a policy on what parts of the Verilog-A code for a model are officially part of the standard. Under long-standing CMC policy, a compliant implementation of a standard model must produce the same currents (dc, transient, and ac) and noises as the reference model. The new policy extends the requirements to operating-point values, noise contributors, terminal names, etc. This talk will discuss the process of developing this policy and the inconsistencies that motivated its development.
[3]	SPICE Modeling of Power Devices Bogdan Tudor Silvaco (USA) Abstract:  Review of Power device SPICE modeling including macromodel development using TCAD data, specific capacitance modeling, and transient model tuning.
	Coffee Break
[4]	Toward physics-based reliability-aware compact models Pieter Weckx, Erik Bury, Ben Kaczer imec (B) Abstract:  This presentation will discuss a range of reliability solutions from test structures to reliability-aware compact modeling. Developing tools and compact models to enable accurate degradation assessment at the design level is imperative for improving end-product PPAC. To maximize potential gains, workload dependence needs to be factored-in, combined with detailed knowledge of the underlying device degradation mechanisms such as Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI), including Self-Heating Effects (SHE). Physics-based understanding of degradation at microscopic / individual defect level will be reviewed. Internally-developed tools and methodologies for assessing and modeling the mean and the variance of device degradation, such as Smart Arrays, Comphy, TCAD, and compact modeling, will be discussed.
[5]	Overview and Parameter Extraction of L-UTSOI Model for FDSOI Technologies Ma Long* and Shuang Cai** Keysight (USA) Abstract:  The Fully Depleted Silicon On Insulator (FDSOI) exhibits excellent electrostatic control and reduced variability for the advanced technologies down to 20nm. L-UTSOI is the to be standardized model that is able to describe the behavior of low-doped ultrathin body and buried oxide fully depleted silicon-on-insulator transistors in all bias configurations, including strong forward back bias. In this paper, we will talk about the L-UTSOI model and introduce the latest extraction flow implemented in Keysight’s Model Builder Program.
[6]	Device Modeling for Neuromorphic Computing with Dynamic Time Evolution Method Lining Zhang, Mansun Chan UST (HK) Abstract:  Memory based neuromorphic computing becomes popular among researchers and compact memory modeling is required for circuit designs. In this talk we will introduce the dynamic time evolution method to reproduce the analog memory nature which is the core feature for the unique application. Continuous programing of the memory in the low-to-high or high-to-low resistance transitions are precisely simulated. The model has been used in the simulations of a phase-change-memory synapse in conjunction with the control circuits as well as the neurons with nice convergence. At the same time, the dynamic time evolution method allows a reduction in the circuit matrix size with a significant reduction of the simulation time for large scale memory applications.
12:00-13:00	Lunch Break and Group Photo
13:00-16:00	MOS-AK Afternoon Session Chair: Bogdan Tudor, Silvaco (USA) and W. Grabinski MOS-AK (EU)
[7]	Latest Developments in the Xyce Large-Scale Analog Circuit Simulator Jason Verley Sandia National Labs (USA) Abstract:  This presentation will provide an overview of the open source analog simulation tool, Xyce, which was designed from the ground-up to perform large-scale circuit analysis. Current capabilities of the simulation tool will be discussed, including the analysis methods, device models, and parallel implementation. An emphasis will be made on the latest developments in Xyce. In the last year, the focus of Xyce development has been in the following areas. First, the calculation of analytic derivatives was added to the Xyce-ADMS backend, resulting in significant performance enhancements. Other performance improvements in the linear solver resulted in improved run times, and a 20% reduction in memory use. The mixed-signal interface was modified to use the VPI (Verilog Procedural Interface) standard, and S-parameter analysis was added. Finally, an HSPICE netlist translation capability will soon be made available to allow easy use of PDKs and circuit designs created for that simulator. The talk will conclude with a discussion of planned developments in the near future.
[8]	An oxide-based bipolar RRAM compact model Meng-Hsueh Chiang, Jia-Wei Lee, Po-An Chen, and Chun-Hsiang Hsu National Cheng Kung University (TW) Abstract:  RRAM (resistive random access memory) has emerged as a promising nonvolatile memory technology due to high density, fast speed, and technology compatibility. Applications of RRAM are also very demanding as RRAM provides opportunities of in-memory and neuromorphic computing with its versatile programming capability and synaptic nature, respectively. All these requires a reliable model that can capture the physical phenomena and can be simply calibrated to limited hardware data, or even can be predictive when technology is not so mature. An oxide-based bipolar RRAM compact model is introduced. Recent findings from technology advances that might enable nonconventional design techniques is overviewed as well.
[9]	Keeping Up with Mextram: 2019 Development Updates with SiGe HBT Circuit Implications Guofu Niu*, Huaiyuan Zhang*, Yiao Li*, Andries Scholten**, Marnix Willemsen***, Wei Chen**** *Auburn University, ** NXP Semiconductors, *** Texas Instruments Inc. (USA) Abstract:  An overview of recent Mextram developments will be given with SiGe HBT circuit application examples, including both Mextram 505.1.0 and 504.13.0 that were released March 2019, as well as on going developments to be included in next release. Mextram 505.1 adds new models for 1) much improved RF linearity modeling, 2) much improved high injection Cbc modeling, 3) much improved substrate current modeling at high VBE, and 4) CB junction leakage and off state breakdown modeling. The background behind the release of 504.13.0 and its implications to oscillator phase noise simulation will be discussed. We will show that the choice of avalanche initiating current has subtle but significant implications on both RF impedance and noise in presence of avalanche, particularly when transistor main current is low.
	Coffee Break
[10]	Characterization of Semiconductor Devices in the High-Frequency Regime Roberto S. Murphy, IEEE EDS DL INAOE, Puebla (MX) Abstract:  As electronic devices reach higher frequencies of operation, the need to trustworthy characterize and model them garners importance. Measurements in the high-frequency regime are not straightforward, however, since the ensemble is prone to experimental errors, which have to be considered and corrected for beforehand. In this talk, I will address the measurement system setup, skimming through measurement uncertainty considerations, setup calibration, and de-embedding aspects. An example of a characterization and modeling run for MOS transistors is also presented. The talk closes with a discussion of future trends and needs in the area.
[11]	Model Evaluation for HiSIM2 3.1.1 Chika Tanaka, Takeshi Naito, Miya Yamamoto, Atsushi Sueoka, and Sadayuki Yoshitomi Memory Division, Kioxia Corporation (J) Abstract:  Model Evaluation for HiSIM2 3.1.1 concerning optimization results with added new model parameter will be reported.
[12]	MVSG model for RF applications: Thermal, Scalability and Parasitic Modeling Xuesong Chen*, Ujwal R Krishna** and Lan Wei* *University of Waterloo (CA), **Texas Instruments Inc. (USA) Abstract:  In this work, we extend the industry standard MIT Virtual Source GaN HEMT (MVSG) model to include layout dependent effects such as scaling of parasitic fringing capacitances, scaling of distributed gate- and channel-resistance, and scaling of thermal network, which target wide periphery FETs for high-frequency (HF) power amplification applications. We have also studied self-heating mechanism and its impact on electrical performance of short gate length GaN HEMTs based on electro-thermal TCAD simulations. Different roles of equivalent channel temperature and max channel temperature are discussed and modeled. Further, we capture the safe-operating area (SOA) of the device by including channel-breakdown in addition to gate-diode breakdown which is useful for high voltage (HV) applications. The modeling approach satisfies Gummel symmetry-benchmarks and is valid for symmetric switch FETs.
[13]	FOSS EKV2.6 Model at GitHub W. Grabinski, IEEE EDS DL MOS-AK (EU) Abstract:  The EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial community of analog integrated circuit design, since its inception in 1996. The model is available as a free open-source software (FOSS) tool coded in Verilog-A. The present paper provides a short review of foundations of the model and shows its capabilities via characterization and modeling based on a test chip in 180 nm CMOS fabricated via Europractice.
16:00	End of MOS-AK Workshop
	International MOS-AK Committee:
Committee	Local Organization Committee  Bogdan Tudor, Silvaco (USA)  Brian Bradburn, Silvaco (USA)  International MOS-AK Board of R&D Advisers Larry Nagel, Omega Enterprises Consulting (USA) Andrei Vladimirescu, UCB (USA); ISEP (FR) MOS-AK Technical Committee MOS-AK/GSA North America Chair: Pekka Ojala, Exar Corporation (USA) Co-Chair: Geoffrey Coram, Analog Devices (USA) Co-Chair: Prof. Jamal Deen, U.McMaster (CA) Co-Chair: Roberto Tinti, Keysight EEsof Division (USA) MOS-AK/GSA South America Chair: Prof. Gilson I Wirth; UFRGS (BR) Co-Chair: Prof. Carlos Galup-Montoro, UFSC (BR) Co-Chair: Sergio Bampi, UFRGS (BR) Co-Chair: Antonio Cerdeira Altuzarra, Cinvestav - IPN (MX) Co-Chair: Roberto S. Murphy, INAOE (MX) MOS-AK/GSA Europe Chair: Ehrenfried Seebacher, AMS (A) Co-Chair: Sanjay Mane, XFab, (D) Co-Chair: Prof. Benjamin Iniguez, URV (SP) Co-Chair: Franz Sischka, SisConsult, (D) MOS-AK/GSA Asia/South Pacific Chair: Sadayuki Yoshitomi, Toshiba (J) Co-Chair: A.B. Bhattacharyya, JIIT New Delhi (IN) Co-Chair: Min Zhang, XMOD Tech, Shanghai (CN) Co-Chair: Kaikai Xu, 电子科技大学 (CN)

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update: Dec.2, 2019  (rev. f)

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