Arbeitskreis MOS-Modelle und Parameterextraktion
MOS Modeling and Parameter Extraction Group Meeting
organized by
W. Grabinski, Motorola and E. Seebacher,AMS
19 November 2001, AMS, Premstaetten, Austria
10:00-10:15 E. Seebacher
W. Grabinski
Welcome and Call to order 
10:15-11:30   Morning Session (Part I)
K. Molnar
MOS Varactor Modeling
High-quality voltage-dependent capacitors (varactors) are especially important for analog RF applications. Recent publications about accumulation-mode MOS varactors summarize the advantages over reverse biased conventional p-n junctions and provide some insight into technology, device physics and discuss the optimization of the quality factor. A possible subcircuit implementation for circuit simulators that exploits the intrinsic capacitance in the industry standard BSIM3v3 model will be presented. Development of the subcircuit and BSIM3v3 model parameter settings will be discussed in detail. The investigation of different geometries resulted in a trade-off between capacitance tuning and quality factor. 
M. Kocher
Realistic Worst Cases (Boundary Models)
For a cost-effective production of integrated circuits, one important aspect is the realistic simulation of the electronic circuits with regard to process variation. We introduce two methods using the concept of the location depth to find device models that allow a fast and realistic simulation. The methods are integrated into an automated generation flow to be applicable in a production and circuit design environment. The statistical methods are validated using measurement and simulation results of typical analog/mixed-signal circuit designs.
11:30-11:45 Coffee break
    Morning Session (Part II)
  M. Bucher
NTU Athens
The EKV v3.0 MOSFET Model
The new Version 3 of the EKV Compact MOSFET Model is presented. The main scope of this model is Analog and RF applications using deep submicron CMOS. The basic charge model formulation closely follows the surface potential based charge-sheet model. The EKV v3.0 model provides coherent modeling of bias and geometrical dependences, from DC to NQS modeling for a broad range of today's CMOS technologies. Furthermore, its analytical formulation not only provides accurate modeling but also effectively supports advanced analog IC design techniques. Key aspects of the EKV v3.0 model formulation are presented and a comparison with the public-domain EKV v2.6 model is provided.
12:30-13:00   Poster Session
T. Gneiting
BSIM4 Modeling Package
Advanced Modeling Solutions presents its newest software package inside Agilent's IC-CAP. The BSIM4 Modeling Package offers a complete DC-to-RF  CMOS modeling toolkit for the latest release of the U.C.Berkeley 's BSIM4 model. AK-MOS members are invited to test the tool with their own process data. 
F. Sischka
Effective Use of IC-CAP 2001 for Fast and Accurate RF Models
( ICCAP-2001, NNMS System)
With the introduction of IC-CAP 2001, modeling engineers can now use the flexibility of IC-CAP even more professionally by using a new, user-definable graphical interface. This is already applied to the new toolkits for BSIM4 and for 1/f noise modeling. In cooperation with the University of Bordeaux, a Hicum toolkit, which matches the existing concept of reusable measurement data for all bipolar toolkits is under development. Nonlinear RF modeling with RF signals up to +40dBm(!) with the link to the new Agilent nonlinear network analyzer N4463A and to harmonic balance simulation in ADS has become possible too. Related to the more general tools in IC-CAP, and related to the open flexible software concept, version 2001 offers enhanced and new work tools for effective and accurate device modeling. Among them are the possibility for centrally located, reusable PEL programs, indirect array addressing for easier scaled modeling, and a new ICCAP_FUNC to change Input/Output/Plot data field entries for selective data management readings. Also, multiple open data files are now possible and selective export of manipulated data (transforms) in the setups. 
N. Campbell
Electromagnetic-Based Modelling of IC Package Parasitics
As signal frequencies continue to rise, the effect of package parasitics becomes increasingly important. In certain applications, to ensure that the packaged die functions correctly, the effect of the packaging must be considered when designing the circuits on the silicon. Electromagnetic analysis provides a means to quantify the parasitics at a early stage in the design. Simple RLC models extracted in this way can be useful at moderate frequencies, but at higher frequencies a full-wave electromagnetic analysis is required in order to capture physical effects such as package resonances and radiation. We present some examples of electromagnetic modelling, showing the complete flow from package layout, through electromagnetic simulation and into circuit and system-level tools such as SPICE or more specialised RF simulators. 
A. Lord
Start-to-Finish On-wafer RF Characterisation
Overview of the basics of making on-wafer calibrations and measurements to 110GHz.  This includes device layout rules and a calibration technique guide to allow accurate and repeatable measurements.  This presentation will assist the user in designing devices for accurate and easy measurements without introducing errors from poor probe pad design, adjacent devices or other possible unknown sources. 
F. Paolini
UTMOST IV: A New Powerful and Flexible Parameter Extraction Environment
13:00-14:30 Lunch
 14:30-15:30   Afternoon Session
D. Foty
Gm/Id Modeling Methodology and Modern Analog Design
A method of interpreting MOSFET behavior is described which is more coherent for modern analog CMOS circuit design. This method supercedes the use of simple but antiquated equations in design, and replaces them with an approach based on the inversion coefficient of the individual transistors in the design.  Measurements and modeling confirm that this method can be used directly to arbitrate among the various countervailing requirements of demanding analog designs. This kind of "deterministic design" is required if the potential of analog CMOS design using deep submicron processes is to be realized. 
A. Napieralski
TU Lodz
Power Devices Modeling
During the last decade the enormous progress is observed in the modelling of IC and systems. It is not through in the case of power devices. The main reason is the distributed character of the phenomena inside the large base of power devices and the thermal problems which in some cases can cause the second thermal breakdown. The key to the good and exact model of power semiconductor structure is the correct model of PIN diode taking into account all the physical phenomena inside this structure. The 2-D or 1-D simulation technique helps us in the creation of the compact models of power devices. In this talk the most important problems in power semiconductor devices modelling will be discussed.
    Organizational topics
15:30-16:00 E. Seebacher
W. Grabinski
Panel discussion / next meeting planning 
  • organization issues 
  • special modeling meetings/tutorials
  • 16:00   Adjourn. End of meeting
    Contents subject to change.©2001 All rights reserved. WG