Abstract: 
Many applications affecting our daily life require devices which can reach very high voltages. This is the case of the motor for washing machines and vacuum cleaners, low consumption lamps etc. All these applications are controlled by a logic translated by 600V with respect to the ground. The device adopted in order to let high voltage world talk with low voltage logic world is a particular component called 'Mickey Mouse' due to its particular shape. This device has been developed in a 0.35um smart power technology, BCD6SOFFLINE, which can integrate at the same time 3.3V/5V/20V CMOS, BJTs, passives, MV MOS and 600V/800V MOS. Since a 'Mickey Mouse' can be composed by several elements, such as linear, curved and ball shaped transistors (hears of 'Mickey Mouse'), the model has to take into account the scalability of the device in terms of linear width, number of curves, and number of hears. Extraction strategy and methodology used to achieve an accurate model will be presented in this work.

Abstract: 
In this work we present selective results using the High-Voltage MOSFET model that is currently developed at EPFL within the COMON project. The model considers the whole HV-MOS device as the in series combination of two analytical physics based models, one addressing the low voltage part and the other the drift region. The main principles of the model are being presented while its predictions are compared with measurements in terms of current and transcapacitances. This hybrid approach is also found to be effective in modelling noise, transients and self heating that are still under developments.

Abstract: 
InP based double heterojunction bipolar transistors (DHBT's) has long been recognized for its potential in high-speed and mm-wave applications. For accurate circuit simulations several InP DHBT specific modeling issues, such as transit-time modulation and collector blocking must be taken into account. Furthermore, effects such as self-heating, breakdown voltage, and collector-emitter voltage offset must also be included for accurate InP DHBT modeling. The small- and large-signal modeling effort for submicron InP/InGaAs DHBT's developed at the Alcatel-Thales III-V Lab will be presented. The DHBT's features a 0.7µm wide hexagonal emitter and emitter lengths ranging from 5 to 10µm. This leads to cutoff frequencies fT in the 250-300GHz range and breakdown voltages BVceo>4.75V. A unique direct parameter extraction procedure for the small-signal modeling is shown to lead to accurate prediction of the measured S-parameters in the frequency range from 40MHz to 110GHz. A scalable electro-thermal large-signal model is then developed based on the UCSD HBT compact model formulation. The scalable large-signal model is shown to predict the DC characteristics of the InP DHBT's as well as the bias dependence of the RF figure-of-merits, fT and fmax. Furthermore, the model is shown to predict the large-signal power characteristics at mm-wave frequencies.

Abstract: 
Modern high speed (RF) transistors encounter certain delay while operated at high frequency or under fast transient. This effect is named as Non Quasi Static (NQS) effect. Physical approach of modeling NQS in both bipolar and MOS devices is similar and utilize partitioning of time varying channel (MOS) or base (HBT) charge over other terminals. Popular MOSFET model BSIM4 combines three modules- charge deficit NQS model, bias dependent gate resistance and substrate resistance models inside NQS modeling. In popular bipolar model HICUM lateral and vertical NQS are examined separately where lateral NQS models emitter current crowding by shunting a capacitor parallel to the bias dependent internal base resistance and vertical NQS models the excess phase shift in dynamic parameters. Unlike BSIM4, HICUM uses the same model for both transient and AC operation which requires an additional minimum phase type sub circuit with a second order Bessel filter. Bias dependent time delay is introduced inside HICUM via VerilogA code in both minority charge and forward current assuming the delay time proportional to the total transit time. A comparison of measurement with respect to simulation up to 110GHz will be presented with emphasis on the phase of h21 and magnitude and phase of y11 and y21.

Abstract: 
Different de-embedding methodologies have been used in the semiconductor industry, starting from the Open-Short, the Three-step method, Four-step method, the Five-step and even the Six-step method. All these methods are based on the measurements of known standards, and using mathematical equations to remove the parasitic contribution. The Five or Six-step methods are scalable, but the programming effort is not negligible. In this work, the two-step de-embedding method has been revisited and a new short structure has been presented called "complete short". Results are compared with respect to a five-step de-embedding method. The measured results show that we get the same de-embedded results up to 110GHz when using the two steps method as by using a five step de-embedding methods. This method reduces the minimum set of test-structures necessary for de-embedding up to 110GHz resulting in less Si area that is needed for accurate de-embedding. But this result is only valid if the design of each test structure is done very carefully considering all the metal layers.