MOS-AK/GSA Workshop Munich

Arbeitskreis MOS-Modelle und Parameterextraktion
MOS Modeling and Parameter Extraction Working Group
MOS-AK/GSA Workshop, April 11-12, 2013 Munich

MOS-AK: Over Two Decades of Enabling Compact Modeling R&D Exchange

MOS-AK/GSA Workshop Host and Sponsors


Lead Sponsor	Sponsor
with the technical program cosponsorship by the IEEE EDS Chapter Germany

Technical MOS-AK/GSA Program Promoters


			The MOSIS Services

2nd Announcement

Venue:	Lehrstuhl fur Technische Elektronik Room: 5325, 5th floor Technische Universitat Munchen Arcisstr. 21 D-80333 Munchen
Agenda:	Spring MOS-AK/GSA Workshop, 2013 April 11, 2013 MOS-AK/GSA Afternoon Session (1st Day) FP7 COMON Project Meeting Networking Evening Event April 12, 2013 MOS-AK/GSA Workshop (2nd Day)
Registration:	free on-line registration
	Workshop Agenda
April 11	Thursday, Afternoon Session
13:00 - 16:00	Oral presentations
	Welcome and Workshop Opening Wladek Grabinski; MOS-AK
	Statistical modeling with backward propagation of variance (BPV) and covariance equations Klaus-Willi Pieper and Elmar Gondro; Infineon Technologies
	Circuit Sizing with Corner Models Challenges & Applications Matthias Sylvester; MunEDA (D)
	Compact Modeling Activities in the Framework of the EU-Funded "COMON" Project Benjamin Iñiguez; URV, Tarragona (SP)
	Effective Device Modeling and Verification Tools Ingo Nickeleit; Agilent Technologies
16:00 - 17:00	Software/Hardware Demos
	MunEDA Framework Applications Tanner TSpice Verilog-A Agilent B1505A Power Device Analyzer / Curve Tracer
	Networking Evening Event
April 12	Friday, Sessions
9:00 - 12:00	Morning Oral Presentations
	Modeling Effects of Dynamic BTI Degradation on Analog and Mixed-Signal CMOS Circuits Leonhard Heiss, Cenk Yilmaz, Christoph Werner, Doris Schmitt-Landsiedel, LTE, TUM (D)
	STEEPER: Tunnel Field Effect Transistors (TFETs) Technology, Devices and Applications Thomas Schulz and Reinhard Mahnkopf, Intel, IMC, (D)
	Current and Future Challenges for TCAD Christoph Jungemann and Christoph Zimmermann; RWTH Aachen University (D)
	Advances in Verilog-A Compact Semiconductor Device Modeling with Qucs/QucsStudio Mike Brinson; London Metropolitan University, London, UK
12:00 - 13:00	Lunch
13:00 - 16:00	Afternoon Oral Presentations
	FDSOI Devices Bentchmarking Bich-Yen Nguyen; SOITEC (F)
	COMON: SOI Multigate Devices Modeling Alexander Kloes; THM (D)
	COMON: FinFET Modeling Activities Udit Monga; Intel, IMC, (D)
	COMON: HV MOS Devices Modeling Matthias Bucher; TUC, (GR)
	End of the Workshop
Committee:	Extended MOS-AK/GSA Committee

No.#18578

update: April 2013 (rev. F)