Workshop Chair: W.Grabinski
Technical Program Coordinator: Prof. H. Iwai 

Abstract: 
Thin-film transistors are the preferred choice for large-area electronic systems, such as displays. However, due mainly to their poor performance, they are usually used only as switching elements. This implies that the main part of the processing power needed to run the displays must be placed outside and fabricated using other technological process, thus increasing the whole cost. There have been some proposals in the literature to increase the performance. Due to the fact that the main limiting factor is the low field effect mobility, a trend is the use of carbon nanotubes (CNT) to raise it. However, there are many technological problems linked to this approach. An alternative is the use of CNT networks, as proposed in the literature. This idea tries to combine the ease of fabrication of TFTs, while at the same time profiting of the high mobility of CNT. In this work, we will propose a compact model for this kind of transistors. Due to the fact that the structure is quite similar to that of an amorphous TFT (a-TFT), we will extend an a-TFT model to take into account the effect of embedding the CNT. The model is compared with experimental measurements, and the fitting is quite good, even when comparing the transconductance.

Abstract: 
This paper is intended not only for the compact model developers and the programmers developing Verilog-A simulator interfaces to support compact models but also for all who are involved in the compact model standardization. ADMS (Automatic Device Model Synthesizer), open code, free-distributed Verilog-A compiler supporting the compact model standardization will be presented In the past, it might be acceptable for a new, automatically-compiled model to run slower than its older hand-coded model version. Compact models written in Verilog A can run reasonably fast if the simulator/interface developers follow recommendations suggested here. Moreover, ADMS Verilog-A compiler can well produce more efficient code than one created manually even by an experience software engineer, particularly if a programmer concentrates only on developing the correct equations for the model. Some of new Verilog-A features supported by ADMS, important for efficient compact model code generation, such as switch-branch (node collapsing as specific case and more significant), initial blocks, initialization on runtime, optional node calculations, noise/frequency description, mfactor will be presented. Possible general implementations of the mentioned features will be discussed and the main results will be delivered.