MOS-AK/ESSDERC/ESSCIRC Workshop in Munich

Workshop Chair: W.Grabinski
Technical Program Coordinator: Prof. H. Iwai

Abstract:
The ongoing trends in MOS scaling have reached limits where further efforts to shrink device size poses a variety of limits in terms of circuit performance. In fact, reducing parasitic effects has become of equal or greater importance compared to increasing "intrinsic performance." New materials are of growing importance to address both aspects of scaling; however, these "improvements" are often offset by making circuit design and compact modeling more difficult. This talk will address many of these issues of MOS scaling and modeling considerations.

Abstract:
PSP102 has been selected by the CMC (Compact Model Council) as the “next generation CMC standard MOSFET compact model” and will be the successor of BSIM4. An introduction into the PSP model will be given covering general features, implemented physical effects and some basics of surface potential based compact modeling. A physical parameter extraction strategy has been derived based on an own developed modeling tool, which gives a very good basis for statistical modeling. First 65nm PSP modeling results will be shown and our developed corner modeling strategy with PSP will be explained as well. Furthermore, an overview will be given about PSP102.2 capabilities to model new material effects and options needed for 32nm, like high-k, metal gates and non-silicon channel (e.g. SiGe-channel).

Abstract:
Presented are the performance-evaluation results of the latest versions 231 and 240 of the surface-potential-based compact MOSFET model HiSIM, which are available in all major commercial circuit simulators. The HiSIM model realizes the difficult combination of two very important practical requirements. These requirements are highly accurate reproduction of electrical MOSFET characteristics down to the 45nm technology node and simultaneously very fast runtime performance in circuit simulation tasks. In particular, the HiSIM model can achieve accurate reproduction of higher-order MOSFET phenomena with a single model parameter set for all device sizes and without new model parameters in addition to those for describing the I-V characteristics. This is a prerequisite for accurate RF circuit simulation and leads to an easy and fast parameter extraction methodolgy. Furthermore, computer runtimes of circuit simulations are the shortest among competing MOSFET models for the same application range.

Abstract:
To address the expense of ownership regarding analog/mixed-signal (AMS) models and improve analog design productivity, an integrated modeling environment known as ModLyng has been developed. This tool, based on the university tool Paragon created at the University of Arkansas, provides substantial utility to the circuit designer, compact modeler, or intellectual property librarian for creating new models, reusing existing models, and porting models to various languages. ModLyng will be presented along with a demonstration of its use in both compact modeling (e.g., PSP) and in behavioral modeling scenarios. In addition to promoting model creation and editing to a more conceptual level and possessing code generation and import technology for standard HDLs, the architecture that ModLyng is based upon is described to illustrate how the tool can be imbedded in design flows, customized for use within organizations, and extended by users.

Abstract:
Silicon-on-Insulator (SOI) MOSFETs are more and more widely used in high-end products, from microprocessors to memories and analog/RF applications. Substrate insulation is responsible for SOI-specific MOS behaviours, generically named floating-body effects or FBE. These may have significant impacts on "hot" device issues such as gate leakage current, short-channel effects, digital and analog performance. Basics and recent findings of FBEs in advanced MOSFETs will be reviewed, in particular in relation with dynamic and frequency-dependent phenomena, with an emphasis on output conductance, self heating, gate tunneling, gate-induced kink and drain coupling through the substrate. Small-signal modelling will be presented. These SOI specific "floating body" phenomena are of special concern for characterization methods, modelling and simulation of new devices and circuits. They deserve attention for correct performance assessment, parameter extraction and application.

Abstract:
Flash memory market has increased exponentially in the last years, mainly driven by the pervasive diffusion of NOR and NAND Flash memory devices in every electronic system. Designing NAND and NOR Flash memories requires large use of Spice-like circuit simulations, which need accurate compact models to be effective. In fact, compact models accurately reproducing memory cells in both DC and transient conditions allow optimizing read and program/erase operations for present and future memory generations, especially in Multi-Level Cells (MLC) applications. In this scenario, we present in this paper a new compact modeling strategy for Flash memories. The Floating Gate transistor, which is the basic building block of both NOR and NAND Flash memories, has been modeled through a sub-circuit comprised of a MOSFET reproducing the Flash memory cell equivalent transistor, a capacitor accounting for the interpoly dielectric capacitance, and some current sources modeling program and erase currents. This modeling approach is scalable and modular; it takes advantage of MOSFET model accuracy; its computation time and parameter extraction are similar to the one of a simple transistor. Compact models of NOR Flash cells and NAND strings developed following this approach will be shown to accurately reproduce real device behavior, making it very appealing for device physicists and circuit designers.

Abstract:
TRADICA© is an integrated expert system linking process and circuit design through physics-based compact modeling. With over 20 years of active and continuous development, the tool offers a variety of features an overview of which will be provided in the presentation:
* (predictive) parameter generation
* parameter extraction
* statistical modeling and support of full-scale statistical simulations
* device sizing
* process optimization
Based on a geometry-scaleable modeling approach the tool facilitates an extremely fast generation of consistent model parameter sets, even during the initial phase of process development, and hence reduces the parameter extraction effort significantly. Approaches and respective fundamentals of each feature will be discussed, focussing on how TRADICA can support and improve work in the areas of technology development and circuit design. Finally, some examples will be presented, illustrating its suitability for aligning process development with circuit product requirements for industry and research.

Abstract:
In this work, our modeling strategy for 32V asymmetric HV MOSFETs fabricated in 180nm High Voltage CMOS process technology using Aurora and Hspice level 66 is presented. The model is validated using the measured characteristics of asymmetric HV MOSFETs. The model shows excellent DC I-V accuracy and good behavior for MOS capacitances. The model also exhibits good scalability over a range of transistor width and length, while the model accuracy of the extracted V_TH and ID_SAT is within 0 to 5% at T=25^oC.

Abstract:
Recently proposed circuit-level models of carbon nanotube transistor (CNT) for SPICE-like simulators suffer from numerical complexities as they rely on numerical evaluation of integrals or internal Newton-Raphson iterations to find solutions of non-linear dependencies or both. Most proposed models rely on an estimation of the mobile charge densities from which the total drain current is derived. Accurate calculation of the mobile charge involves integrating the densities of states over the number of allowed energy levels using the Fermi probability distribution. As the total drain-source current is driven by the self-consistent voltage, which comprises i.a. the drain-source bias voltage as well as potential induced by the non-equilibrium mobile charge injected from the source and drain, a solution of non-linear algebraic equations is necessary to calculate the drain current. Numerical evaluations of integrals and iterative solutions of non-linear algebraic equations (usually by the Newton-Raphson approach) are time consuming and may be impractical in simulations involving large numbers of CNT devices of varying parameters as well as CNT interconnects. Recently approaches have been proposed that eliminate the need for numerical integration when calculating the charge densities in CNTFET through the use of piece-wise linear approximation. This paper gives an overview of existing modelling approaches but also presents a new methodology that builds on the effective employment of linear and quadratic approximation to accelerate the CNT model speed when evaluating the source-drain current of the CNT. Results show a dramatic speed up of up to almost four orders of magnitude compared with state of the art classical CNT models.

Workshop Agenda: Friday, 14 September 2007 in Munich
Workshop Chair: W.Grabinski Technical Program Coordinator: Prof. H. Iwai
Morning Session 9:00-11:00 Oral presentations 10:00-10:30 (coffee break)	Poster Session 11:30-12:00 Posters 12:00-13:00 (lunch)	Afternoon Session 13:00-16:00 Oral presentations 14:30-15:00 (coffee break)