Workshop Chair: Dr. W.Grabinski
Technical Program Coordinator: Prof. H.Iwai

Abstract: 
With rapid growth in the RF wireless communications market, demand for high-performance with low-cost RF solutions is rising.. This advanced performance of MOSFETs is attractive for RF circuit design in view of a system-on-chip realization, where digital, mixed-signal baseband, and RF transceiver blocks would be integrated on a single chip. Therefore, the necessity of precise models, which can accurately predict the behavior of MOSFET devices in RF region is required. Many reports on RF modeling have been written, especially on MOSFETs with SiO2 gate insulator. However, RF modeling of future generation MOSFET with high-k gate insulator has rarely been reported. In our report, we focused on the RF performance of Sub-100 nm High-k MOSFET with HfSiON as gate insulator material. High-k material, which has high dielectric constant enables the gate insulator to be thick without loosing the gate capacitance and lowering the gate leakage current. One of the concerns in High-k MOSFET in RF region is that the gate capacitance descends due to dielectric dispersion. By measuring the DC characteristics and S-parameter of finger-gated MOSFET up to 40 GHz, we extract the parameters using equivalent circuit model. We will present the gate capacitance estimation at high frequency and argue over High-k MOSFET in RF region.

Abstract: 
A simulation study was performed for implantation of P and B into a Novolac-based positive type photoresist for the use in submicron processes. The purpose was to determine the minimum thickness needed to stop the implantation in the resist, while allowing minimal line opening CD in the resist for doping of a required circuit part. Such stopping-power data are either not available for this resist type in the literature or from the manufacturer, or the general data in the literature and the textbooks require too thick resist. Thick resist cannot be applied due to limited aspect ratio. Critical parameters in this Monte-Carlo simulation are resist-layer density after the bake and the compound correction. Density is precisely measured. The compound correction is determined by comparison of the simulation results against the experimental penetration into the Si-bulk measured on a short loop with implantation into stack resist/SiO2/Si-wafer (using surface-charge analyzer). Optimum minimum thickness for required (but not larger) process margin is applied on a full-flow lot in a deep-submicron CMOS/EE process. Fine-variation-splits in resist thickness confirm very accurate calibration of the MC simulation with the experimental short-loop.

Abstract: 
Device modeling for circuit applications faces conflicting requirements of accuracy, efficiency, and development time. The method of generation of equivalent circuits has been applied to one-dimensional p-n junctions and bipolar transistors. This approach has been assessed on a number of a practical circuits, with a comparison of accuracy gain and the performance. The method is based on the calibration on a simplified equivalent-circuit model on simulation results, and can achieve an optimum balance of model complexity, accuracy, and generality. Benchmarking data include some typical digital and analog circuits.

Abstract: 
In this paper, we have presented 2-D scalable models for the threshold voltage, DIBL effect and the subthreshold swing for Gate All Around (GAA) and Double Gate MOSFET (DG) in order to investigate the scalability limits of these devices. Good agreement was observed with numerical 3-D simulations for a good range of channel lengths, diameters, and drain-source voltage values (Fig. 1). The models have been used to predict and compare the performances of downscaled GAA and DG MOSFETs. We have observed that to reach a given performance (represented by a fixed value of the subthreshold swing, S=20 mV), the GAA MOSFET, can have a 33% shorter channel length than the DG MOSFET.

Abstract: 
We present a novel, compact model for cylindrical gate-all-around (GAA) MOSFETs, with emphasis on short-channel devices of nanoscale dimensions. In the subthreshold regime, the electrostatics of such devices is dominated by the capacitive coupling between the electrodes. Previously, we have successfully analyzed the 2D electrostatics of double gate (DG) MOSFETs using conformal mapping techniques. Here we show that the same solution applies to the cross-section through the axis of the cylindrical GAA by performing an appropriate compensation for the difference in gate control of the two devices. In fact, the major difference between the two is a length ratio parameter, which can be determined analytically from the so-called characteristic lengths ?DG and ?GAA of penetration of electrostatic influence from the source and drain towards the device center for the DG and GAA geometries, respectively. In a straightforward procedure for modeling a GAA MOSFET of length L, we calculate the potential distribution for a DG device with length L' = L?DG/?GAA, and then compress this distribution uniformly in the length direction using the scaling factor ?GAA/?DG and assign it to the GAA MOSFET. In strong inversion, the electrostatics of the DG and the GAA MOSFET close to the channel barrier approaches the long-channel behavior. The potential distribution is then dominated by the inversion charge, allowing it to be self-consistently described by a 1D Poisson's equation in Cartesian (DG) or polar (GAA) coordinates. The drain current, considering the drift-diffusion mechanism, then approaches that of a long-channel device. The electrostatics and the drain current calculated with the present model are in excellent agreement with numerical simulation performed with the Atlas device simulator from Silvaco. The model also scales well both with respect to gate length and aspect ratio (L/tSi).

Abstract: 
We present a novel, 2D compact model for double gate (DG) MOSFETs, with emphasis on short-channel devices of nanoscale dimensions. In the subthreshold regime of a lightly doped DG MOSFET, the electrostatics of such devices is dominated by the capacitive coupling between the electrodes. In this case, the Laplace equation of the rectangular body cross-section, including the gate insulators, can be precisely analyzed using conformal mapping techniques, where the body is mapped into the upper half-plane of a transformed complex plane using a Schwartz-Christoffel transformation. In this plane, an analytical solution of Laplace's equation exists, which can easily be transformed back to the real plane. This solution inherently contains the dependency on the device geometry and on all combinations of applied voltages at the four electrodes. Hence, short-channel effects such as DIBL are included. Figure 1 shows an example of a modeled subthreshold potential distribution of a DG MOSFET (L = 25 nm, tSi = 12 nm) with an applied drain-source voltage. Figure 2 shows a comparison of between the model (solid curves) and numerical simulations (circles) for subthreshold potential distributions along the source-to-drain symmetry axis at different drain voltages. In strong inversion, the electrostatics of the DG MOSFET near the channel barrier approaches the long-channel behavior. The potential distribution is then dominated by the inversion charge, allowing it to be described by a 1D Poisson's equation. The drain current, considering the drift-diffusion mechanism, then approaches that of a long-channel device. The electrostatics and the drain current calculated with the present model are in excellent agreement with numerical simulation performed with the Atlas device simulator from Silvaco.

Abstract: 
This poster will describe an explicit compact model of Independent Double Gate(IDG) MOSFET with undoped channel. The model includes new physical short channel effects: the subthreshold slope and the Vth roll-off are expressed with explicit expressions. These new compact expressions are based on an approximation of the surface potential derived thanks to the superposition theorem. The validity of this model will be demonstrated by comparisons with Atlas simulations. The model was implemented in VerilogA in order to test it and to design circuits. Circuit results of a mixer and an inverter will be also presented.

Abstract: 
In this paper we present an improved compact OTFT model which extends our previous model into the subthreshold regime. In the original model, the field effect mobility (uFET), saturation voltage (VDSat) and current (IDS) were expressed by simple expressions. In order to extend the applicability of the model to the subthreshold regime. The use of this expression thus reproduces the observed polynomial behavior of the subthreshold current in OTFTs, instead of the classical exponential behavior in crystalline MOSFETs. In deep subthreshold, VGSX tends to zero and IDS to I0 as it should, while in the above threshold regime, VGSX tend to VGS-VT, thus recovering the previous model. Extraction of the model parameters has been performed by using a fuzzy logic extension of the original procedure in literature. These techniques allow to use expert knowledge about the model behaviour into the parameter extraction method, thus simplifying the task. The experimental and modeled transfer characteristics (for a pentacene OTFT from Infineon) are compared.

Abstract: 
Up to now, the EKV has been popular mostly among low power analog circuit designers, because of its superior modeling of the weak and moderate inversion areas of operation of the MOSFET. The 'level of inversion' concept is one of the key elements of the EKV model. The design methodology based on the 'level of inversion' is a very logical and efficient method for designing analog circuits, and not only for very low-power circuits, but also for all applications. The basic 'level of inversion' equation can be used to size transistors with hand calculations, and to easily optimize circuits when using software tools. The designer can now move to the full model to perform simulations, with confidence that he will get accurate results in all modes of operation of the MOSFET. The model can be extracted from transistor data, or estimated from the foundry's model and process specification.

Abstract: 
We compare a new charge based model, EKV3 with the BSIM3 and BSIM4 for the MOSFETs. Model parameters has been extracted in 0.35 um CMOS technology for the EKV3 and BSIM3, and 0.18um CMOS technology for the EKV3 and BSIM4. Parameter extraction strategy has been implemented in ICCAP. Physical modeling, like a short channel effects, narrow channel effects, drain induced barrier lowering, mobility reduction due to vertical field, carrier velocity saturation, channel length modulation, polysilicon-gate depletion effects, quantum mechanical effective on gate oxide thickness, gate leakage current, and overlap capacitance is presented for the both models. Geometry scalability of EKV3 is verified for both the technology. Worst case corner modeling is also investigated and the result is presented. Finally, model benchmark test has been performed for the EKV3 model. EKV3 is a self-consistent and charged based physical model for new generation MOSFETs. Most of the model parameter is directly linked to the process control monitoring and then parameter extraction is much simpler. EKV3 has less parameter set while offering similar scaling ability as BSIM3/4. Also, symmetrical test has been passed successfully for both DC and CV characteristics.

Abstract: 
EKV3.0 model provides very good accuracy between weak and middle inversion region. It is very important features for the analog IC design. To demonstrate the capability of EKV3.0 compact model, we will present EKV3.0 design kit for TOSHIBA’s 110nm RF-CMOS technology. It is sub-circuit based model consisting of EKV3.0 as a core transistor and additional passive elements, which describe the high-frequency effects. This provides good scalability from DC to RF(~20GHz) region with small numbers of EKV3.0 model parameters compared to BSIM3. EKV3.0 model parameter extraction has completed by the measurement of conventional transistor structures and multi-finger devices dedicated to the RF front-end circuit. This extraction flow will be shown in this presentation. To demonstrate further capability of EKV3.0 for high-power application, we will show the result of 2.5GHz Load-Pull measurement.

Abstract: 
Pinch resistors are devices for high voltage applications typically used as high rsh resistors, constant current sources or voltage limiters. Unfortunatelly existing simulators don't provide precise built-inmodels for such components - standard jfet model, usually derived from Schichmann & Hodges FET model is usually not sufficient. This poster is demonstrating very precise models of voltage dependent resistors from light voltage dependent resistors to jfet-like pinch resistors.

• 1) Spice-like voltage dependent resistor model for low doped voltage dependent implant resistors
• 2) VerilogA model for very low doped implant resistors
• 3) VerilogA model for pinch resistors
• 4) Using of very low doped implant resistor model for the modeling of LDMOS quazisaturation effect

Abstract: 
Statistical modeling in the design of today’s high performance integrated circuits is a necessity to produce competitive products with short development time. The use of backward propagation of variance has proven its worth among other approaches proposed for the statistical modeling. In order to make the statistical models relevant in the course of process lifetime, feedbacks to manufacturing must be established and process control tools developed. The goal of the poster presentation is to demonstrate basic features and links between the following tools:

• Tool 1: to define targets and other statistics in the way complying to industry standards
• Tool 2: to create statistical models available in design kits
• Tool 3: to run Statistical Process Control over a critical set of PC data (SPC on PC)
• Tool 4: to perform regular process monitoring verifying the validity of statistical models

Abstract: 
High voltage mos transistors usually have a drift zone in the drain region. The conductivity of this drift zone is strongly dependent on the flowing current and gate voltage. Thus it has generally to be modelled with a variable resistance representing the effects on the current. The goal of this work is to show a phenomenological macro model including AC modelling. The model is restricted to a lumped element sub-circuit, which can be processed by a standard spice simulator. A drain resistance can be described by a behavioural source and a resistance in series. The source could be a current or voltage source controlled by drain current and gate voltage. The example discussed in this paper describes a sub-circuit containing a current source with a resistor in series as well as a model of the voltage dependent gate to drain capacitance. One of the most important goals of development was a fast convergence of the transient simulation. This was achieved by a restriction of the mathematical formula for the current function. The model is tested by means of a ring oscillator. The results have been satisfactory for DC, AC as well as transient analysis.

Abstract: 
This paper reports the results of a detailed study of a commercial implementation of the Line-Reflect-Reflect-Match (LRRM) vector network analyzer calibration method with automatic load inductance correction. Limitations in applicability for non-offset standards and when the Line (Thru) standard is electrically long and/or the load inductive reactance is large are examined. An enhanced LRRM (eLRRM) algorithm has been developed providing superior and more predictable results for these less frequently encountered cases. eLRRM is available in a commercial VNA calibration software product.

Abstract: 
CST MICROWAVE STUDIO® (CST MWS) is a specialist tool for the fast and accurate 3D EM simulation of high frequency problems. Along with a broad application range, CST MICROWAVE STUDIO® offers considerable product to market advantages: Shorter development cycles - Virtual prototyping before physical trials - Optimisation instead of experimentation. CST MWS is also recommended to be employed in modeling integrated circuit environments. This poster presents different applications and in particular the case in which CST MWS and Agilent ADS have been successfully employed in OEIC driver design - an example of a high speed analog/broadband IC application. The package model was imported from Agilent momentum and the model was simulated upto a 100 GHz in CST MWS. The resulting eye diagrams of the driver design from CST MWS are compared with those from Agilent momentum and other test cases.

Abstract: 
This paper presents a fully customizable compiler approach for implementing compact models defined in Verilog-AMS into Spice3-like simulators. Recently, there has been an on-going debate over the best way to release the source code of compact models. Should the release be a set of behavioral equations rather that just Spice3 C code? Judicious choice of compiling techniques makes the question irrelevant. This paper introduces the latest version of the ADMS system. It discusses some general guidelines to build Spice3 device compilers using the ADMS system, with limited loss in speed performance and significant gain in code reliability and maintainability. We conclude with a case study: implementation of the BSIM3 model in Freescale's in-house circuit simulator Mica©, which gives the same results as the handcrafted version of the model and has only an 8% performance loss.

Abstract: 
What are the technical challenges that have to be overcome when developing the next state-of-the-art circuit simulator? And what does the future hold for circuit simulation technology? Today’s requirements for high performance networking, consumer electronics, defense and telecommunications IC’s are driving new requirements for circuit simulation. Although it was commonplace to trade accuracy for speed and/or speed for capacity a few years ago, it is no longer acceptable to do so today. Furthermore, today’s applications are demanding new approaches that include multiple simulation domains and varying levels of circuit detail. In this presentation, we will discuss the technological advances that Ansoft has made to enable efficient circuit simulation solutions across multiple simulation domains and varying levels of circuit detail. Advancements in timestep control, multi-tone harmonic balance, accurate noise analysis, and causal passive S-parameter implementation will be discussed. Circuits that highlight Ansoft’s ability to solve very large problems accurately and efficiently will be shown and when possible, measurement vs. simulated data will be shared. The talk will conclude with a discussion of the continued research and technical challenges Ansoft is focusing on as circuits become smaller and operating speeds increase.