Arbeitskreis
MOS-Modelle und Parameterextraktion MOS Modeling and Parameter Extraction Working Group MOS-AK/ESSDERC/ESSCIRC Workshop Compact Modeling for Emerging Technologies Friday, 22 September 2006 Montreux Convention and Exhibition Center |
Poster Session | ||
Workshop
Chair: Dr. W.Grabinski
Technical Program Coordinator: Prof. H.Iwai |
Technical Program Promoters |
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Sponsors |
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Poster Session | ||||||
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11:00-12:00 | Poster Session - Chair: Prof. Wieslaw Kuzmicz, TU Warsaw and Dr. Gerhard Knoblinger, INFINEON | |||||
1. | High Frequency Model of
Sub-100nm High-k RF CMOS Masayuki Nakagawa1, Jaeyeol Song1, Yasuo Nara2, Mituo Yasuhira2*, Fumio Ohtsuka2, Tsunetoshi Arikado2**, Kunio Nakamura2, Kuniyuki Kakushima1, Parhat Ahmet1, Kazuo Tsutsui1 and Hiroshi Iwai1 1 Tokyo Institue of Technology,4259,Nagatsuta-cho,Midoriku,Yokohama,226-8502,Japan 2 Semiconductor Leading Edge Technologies, Inc.(SELETE),Japan * Current affiliation: Matsushita Electric Industrial Co.Ltd., Japan **Current affiliation: Tokyo Electron LTD., Japan |
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2. | Monte Carlo simulation and
experimental study
of stopping power of lithography resist and its application in
development of a CMOS/EE process Predrag Habaš, Roman Stapor, Alexandre Acovic and Maurice Lobet; EM Marin |
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3. | Application of
physics-based device models for circuit simulation Victor Spitsyn and Ilya Lisichkin, Cadence, Moscow |
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4. | Analytical Predictive
Modeling for the Scalability Study of Double-Gate and Gate-All Around
MOSFETs Hamdy Abd El-Hamid1, Benjamin Iñíguez1, Jaume Roig2 1.Departament d’Enginyeria Electrònica, Elèctrica i Automàtica; Escola Tècnica Superior d’Enginyeria; Universitat Rovira i Virgili; 43007-Tarragona, Spain. 2.LAAS / CNRS, 7 avenue du Colonel Roche, 31077 Toulouse Cedex 4, France |
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5. | Development and
Verification of a Precise Compact Model for Short-Channel
Gate-All-Around MOSFETs H. Børli, S. Kolberg, and T. A. Fjeldly UniK – University Graduate Center and Norwegian University of Science and Technology, N-2027 Kjeller, Norway. |
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6. | Verification of a Novel 2D
Compact Model for Short-Channel Double Gate MOSFETs S. Kolberg, H. Børli, and T. A. Fjeldly UniK – University Graduate Center and Norwegian University of Science and Technology, N-2027 Kjeller, Norway. |
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7. | Explicit Threshold Voltage
Based Compact Model Of Independent Double Gate (IDG) MOSFET Including
Short Channel Effects Marina Reyboz, Olivier Rozeau, Thierry Poiroux, Patrick Martin and Jalal Jomaah CEA, Grenoble |
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8. | An Organic TFT Compact
Model Including the Subthreshold Regime R. Picos1, B. Iñiguez2, E. García-Moreno1, R. García2, M. Estrada3 1.University of Balearic Islands, Spain 2.Universitat Rovira i Virgili, Tarragona, Spain 3.CINVESTAV, Mexico DF, Mexico |
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9. | Low-power circuits and
beyond; a designer's prospective on the EKV model and its usage Patrick Mawet; Micro Encoder, Inc. Kirkland, WA, USA |
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10. | Comparison of MOS Model
EKV3 with BSIM3 and BSIM4 B. Senapati and E. Seebacher austriamicrosystems AG, Schloss Premstaetten, Austria |
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11. | EKV3 design kit for 110nm
RF-CMOS S.Yoshitomi, TOSHIBA Corp. Semiconductor Company, Japan |
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12. | Modeling of very low doped
and pinch resistors Stanislav Banas, Vladimir Stejskal; ON Semiconductor, Czech Republic |
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13. | Statistical modeling Jiri Slezak; ON Semiconductor, Czech Republic |
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14. | Lumped Element Behavioural
High Voltage MOS Model Sebastian Schmidt and Matthias Franke; X-FAB Erfurt Germanny |
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15. | An Enhanced
Line-Reflect-Reflect-Match Calibration Leonard Hayden, Gavin Fisher(presenter), Cascade |
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16. | CST MWS: EM Simulations
and Modeling Jérôme Mollet and Ralf Ehmann; CST GmbH, Darmstadt |
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17. | ADMS - a fully
customizable Verilog-AMS compiler approach Laurent Lemaitre, Freescale, Geneva |
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18. | Recent Advancements in
Circuit Simulation Technology Xavier Le Goaer, Ansoft France SAS |
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12:00 | End of the poster session |
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