J. Ramos, A. Mercha, W. Jeamsaksiri, D. Linten1, S. Jenei,
S. Thijs, A.J. Scholten2, P. Wambacq1, I. Debusschere, S. Decoutere
IMEC Leuven, 1 Also with the Vrije Universiteit Brussel,
2Philips Research Eindhoven
A 90nm RF CMOS technology supported by device modeling and circuit
demonstrators
Ever increasing
computation requirements have lead CMOS technology through a rapid
downscaling. As a consequence, its speed limitation has been overcome,
turning CMOS technology into a serious competitor with Bipolar or III-V
technologies in Radio-frequency (RF) applications. This fact opens a
new window in which, for the first time, a fully integrated CMOS
Mixed-Signal System-on-Chip is made possible. RF operation introduces
new challenges in the CMOS modeling. In this work we present a 90nm RF
CMOS technology featuring 70nm physical gate length MOSFETs and high Q
passive devices. Suitable RF models for active (MM11 compact model) and
passive (In-House) devices enabled designers to demonstrate circuits
operating at 5GHz.
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Ahmed Alabadelah, Dominique Schreurs, Cornell van Niekerk*,
and Bart Nauwelaers; K.U.Leuven and *University of Stellenbosch
Methodology to validate and inter-compare RF models
In most of the
papers, researchers show what they would like to show when they compare
their model with measurements, which can mislead the reader when
ignoring other significant measurements. Several standardization
efforts were initialized, like the work that has been done by Compact
Modeling Council (CMC), but was limited to DC, CV and temperature
measurements. Other paper compared nonlinear MESFET models, but there
was no real winner. Within the framework of TARGET, we will compare,
power devices and power amplifier models based on several tests. We
found out that any “good” nonlinear model should pass five
tests, which
are: 1- DC test, 2- CV test, 3- RF (S-parameters) test, 4- Soft
nonlinearities test (Inter-Modulation Distortion (IMD)) test, 5- Hard
nonlinearities test (Harmonics).
V.A. Gergel, M.N. Yakupov; Russia Academy of Science
Quasi-hydrodynamic extension of gradual channel and charge sheets
approximations of MOSFET models
In
sub-deep-micron transistors the crucial role plays electroheating of
carriers with two-dimensional distribution of high electric fields (up
to 10^5-10^6 V/cm). And so the modern MOSFETs models which are based on
drift-diffusion equations with gradual channel and charge sheets
approximations and contain hundreds of adjustment parameters can be
treated as a possibility for analytic calibration of experimental
dependences. From the other side there are a lot of complex tools used
to simulate MOSFETs characteriscs from energy transport equations, but
they are very time consuming and complicated for the verification of
dependencies and model parameters. We propose to use quasi-hydrodynamic
description of electron drift with account for mobility and energy
relaxation time dependencies of electron temperature and formulate
semi-analytic extention of gradual channel and charge sheets
approximations of MOSFET models. We discuss some possible applications
of this techinque on sectioned channel and gap-mismatching
semiconductor structures and show how it describes a super-speed
electron drift which is known as overshoot effect.
Fadhila Haned*, Mohamed BenChouikha*, Andre Baguenier Desormeaux**,
Georges Alquié** LISIF, Université Pierre et Marie Curie*
Cadence Design Systems SAS France
Verilog-A behavioral models of optoelectronic devices for Color
Sensor Design
The recent
advancements in the areas of CMOS sensors have lead to low-power,
low-noise, portable and low coast imaging systems. However, in color
imaging fields, CMOS sensors are still using photodiodes and RGB
optical filters combination. This entails many limitations to the color
imaging sensor performances. We reported that buried junctions color
detectors represent good alternatives to overcome these limitations.
However, successful design of integrated color sensor using buried
junction detectors, such as active pixel circuits for multispectral
cameras and spatial applications, requires an accurate knowledge of the
color detectors behaviors. Unfortunately, circuit simulators do not
provide models for these devices. Further, only voltage and current
sources are available in CAD tools. In order to overcome these
limitations and make the designer task more flexible, an Optoelectronic
library under CADENCE design tool has been developed. This library has
been obtained by implementing in Spectre simulator the behavioral
models of the Buried Douple pn Junction (BDJ) device and of a set of
optical sources. These modules, BDJ and the optical sources, have been
described using Verilog-A language and their cellviews have been
created using the Affirma Analog Circuit Design Environment. By a
number of different sources, the designer can choose an optical
stimulus spectral distribution corresponding to a specific application.
He can also select from the source cellview the total power incident on
the BDJ surface. The simulation results of the BDJ spectral response
and dark current obtained under Affirma Analog Circuit Design
Environment give best fit to experimental data. Furthermore, series of
test simulations on active pixel sensor architectures were carried out.
We noted the absence of convergence errors or mathematical faults
during stationary DC and transient simulations. The results confirm the
robustness of our optoelectronic CAD models.
Patrick Mulder, Evelyn Grossar; IMEC
Compact modeling of digital circuits in deep-submicron CMOS
In the past, the
ITRS roadmap for microprocessors was mainly driven by the system clock
frequency. However, for Internet or network applications not the CPU
frequency but the total cost of the system is of critical importance.
Today, the cost is determined at design-time by silicon area and IP
reusability, whereas at system-run-time it is the standby- and
active-power consumption. The need for circuit compact models is
twofold: As different MOS device concepts and process technology
options become available, it is interesting to quickly predict effects
on system-level without making an expensive maskset. Second, for
applications where power consumptions is critical, accurate compact
models are necessary for optimum timing at low-voltage operation. The
presentation will present some results on some basic digital circuits.
R. F. Scholz, B. Senapati, W. Kissinger, E. Matthus and S. Jaetzlau;
IHP Microelectronics
A Differentiated MPW and Prototyping Service with Advanced RF
Performance
IHP offers 0.25
µm SiGe:C BiCMOS technologies with high RF performance and high
voltages for MPW & Prototyping. The service is also available via
Europractice. Technologies include HBTs with peak frequencies up
to 200 GHz as well as with breakdown voltages up to 7 V. They target
wireless and broadband applications incl. fiber-optic communication and
automotive sensors. Complementary HBT modules as well as modules with a
still higher performance are under
development. Technologies with integrated
complementary RF LDMOS modules offer devices working at fmax up to
50(22) GHz for n(p) type. Breakdown voltages up to 26(-13.5) V are
reached. These technologies target system-on-chip solutions for power
amplification, power management, DC to DC converters, and drivers for
motors and LCD displays. Devices with higher breakdown voltages are
under development.
Rob Streeder, Agilent
Measurement Solutions without Compromise:
Agilent 41000 Series, Integrated Parametric Analysis and
Characterization Environment (iPACE)
Agilent is very pleased to announce the new generation of
semiconductor parameter analysers, with several new products of high
measurement accuracy: The Agilent 41000 Series. The main benefits are
that it is a fully integrated solution, and ready to use with semi auto
and auto probers. It also provides highly accurate IV-CV measurements
(fA level&fF level). The new semiconductor parameter analyzer 4157B
has an improved SMU technology to achieve atto Amper level measurement,
where Agilent created the concept of Atto Sense Unit, that perform aA
level, with an integrated switch to perform IV-CV measurements without
any reconnection. The new switching matrixes B2200A and B2201A provide
more inputs ports with low current and low CV capabilities. They have
14 inputs port (8 triax and 6 BNC) to evaluate advanced devices with
high performance.
Marc Vanden Bossche, NMDG Engineering bvba
A new dimension to transistor characterization and modeling through
large-signal network analysis NMDG Engineering
Through
large-signal network analysis it is possible to study the
characteristics of transistors in small - signal mode under matched
conditions and in large - signal mode under mismatched conditions. The
applied signals can go from a continuous wave to a modulation signal.
This type of analysis provides the process and modeling engineer all
the means to make sure that the transistor is reliable under realistic
conditions and that the models will probably function when used by
designers in realistic conditions.
Marek Mierzwinski; Tiburon Design Automation,
Santa Rosa, CA
New Capabilities for Verilog-A Compact Device
Models
The purpose of
the poster is describe how new advances in implementation of the
Verilog-A language in analog simulators provides an ideal development
and release process for compact models. The key point of the
presentation is that while Verilog-A is a natural language for compact
models, end-users will not accept it unless it is completely
transparent to them. Verilog-A models should have no short-comings or
restrictions compared to native, c-coded models. Most analog simulators
already support Verilog-A for behavioral modeling. The Tiburon
implementation of this standard language relies on close collaboration
with simulator vendors. The RTE is an application-program interface
(API) that connects the model to the simulator in a way such that no
simulator functional is lost. Verilog-A has been shown to be a capable
and natural language for compact model development. It relieves the
developer of many complex and mundane tasks, allowing them to
concentrate on model development. Verilog-A has become more popular and
is now widely supported in most analog simulators.
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R.Müller, J.Kusterer, P.Schmid, K.Janischowsky, F.J.
Hernandez-Guillen, A.Denisenko, E.Kohn; University of Ulm
Using CVD-diamond in MEMS technologies
Diamond
can
be
used
as universal MEMS material with extreme properties in many
respects, namely hardness, Youngs modulus, fracture strain, thermal
conductivity and chemical inertness. In addition, it is a wide-band-gap
semiconductor and can be highly insulating, semiconducting and
quasi-metallic by doping. It represents a multi-functional material,
substituting complex material stacksIn this talk, we will concentrate
on nanocrystalline diamond films, which have been grown by CVD on
100-oriented silicon. Their mechanical properties may be highlighted by
a fracture strength of more than 4.0 GPa and Youngs moduli of up to
1020 GPa. Variation in deposition parameters allow to tailor the
vertical and horizontal stress distribution from heavily strained to
virtually stress free. As an example, out of the field of RF-MEMS,
microswitches will be discussed. This will be firstly an
electrostatically driven RF microswitch for high power application,
which can operate up very high temperatures (650°C) and second a
thermally driven bi-stable microswitch with very low switching voltage
(1.3 V) and high actuation force. Secondly, we will address the field
of fluidics and chemistry with a thermally actuated diamond micro
membrane pump and a bubble jet element which has been used in the
synthesis of oligonucleotides and spotting. This structure has been
refined to a point where the liquid is only in contact with diamond.
This may enable further novel applications like patterned etching by
dispensing highly aggressive liquids.
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