| Arbeitskreis
MOS-Modelle und Parameterextraktion MOS Modeling and Parameter Extraction Working Group MOS-AK/GSA Workshop March 16-18, 2012 India |
MOS-AK:
Enabling Compact Modeling R&D
Exchange
| In Collaboration with |
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 INDIAN NATIONAL ACADEMY OF ENGINEERING |
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| MOS-AK/GSA Workshop Sponsors |
| Platinium Sponsors | |
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| Gold Sponsors | |||
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 DIT |
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| Silver Sponsors | |||
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| Technical MOS-AK/GSA Program Promoters |
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  IEEE EDS Chapter Delhi |
 The MOSIS Services |
| Technical
Workshop Program |
| Venue: | Jaypee Institute of
Information Technology (JIIT), A-10, Sector-62, Noida (U.P.), India Phone: 0120-2400973-976, 2400987 |
| Technical Workshop
Program |
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| March 16, 2012: MOS-AK/India Workshop | |
| Time | Program |
| 08:30-09:30 | On-Site Registration |
| 09:30-10:30 | Inaugural Session and Launching of MOS-AK/GSA, India |
| 10:30-11:00 |
Tea Break |
| 11:00-13:30 | Technical
Session: I - Chair: Wladek Grabinski, MOS-AK/GSA |
| I-1 |
Surface
Potential Based Modeling: HiSIM Compact Model Family Mitiko Miura-Mattausch, Hiroshima University, Japan |
| I-2 |
Hardware
Accelerated Interconnect Capacitance Extractor for VLSI Design Narain D. Arora, Silterra, Malaysia |
| I-3 |
BSIM Models:
From Multi-gate to the symmetric BSIM6 Yogesh Chauhan, UC Berkeley, USA |
| I-4 |
Compact Model Application to Statistical Variability and Reliability Studies Xing Zhou, NTU, Singapore |
| 13:30-14:30 | Lunch |
| 14:30-15:00 |
MOS-AK/GSA Poster Session |
| 15:00-15:15 | Tea Break |
| 15:15-17:45 | Technical
Session II - Chair: Rajamohan Varambally, ST Microelectronics, India |
| II-1 |
MOSFET Compact
Modeling Extensions for Circuit Simulation: A perspective from Industry Andre Juge (STM), France |
| II-2 |
Benchmarking of High Voltage (HV) MOS Transistor
Models Ehrenfried Seebacher, AMS, Austria |
| II-3 |
High Voltage
(HV) MOSFET Technology Models & Applications Vaidyanathan Subramanian, IBM, India |
| II-4 |
General
Methodology to Develop Statistical Compact MOSFET Models for VLSI
Circuit Simulation Samar Saha, SuVolta, Inc., USA |
| 19:00 onward |
Networking Dinner |
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March 17, 2012: MOS-AK/India Workshop |
| Time | Program |
| 09:30-11:30 | Technical
Session III - Chair: Narain Arora, Silterra,
Malaysia |
| III-1 |
Verilog-A
Compact Model Standardization Wladek Grabinski, MOS-AK/GSA, EU |
| III-2 |
SPICE to
QucsStudio via Qucs: An international attempt to develop a
freely available GPL RF design, compact modeling, simulation, data
processing and manufacturing development environment for engineers Mike Brinson, London Metropolitan University, UK |
| III-3 |
An Automatic
Parameter Extraction Procedure for an Explicit Surface Potential Based
Compact Double Gate MOSFET model Thomas Gneiting, ADMOS, Germany |
| III-4 |
Insights into
the Design and Optimization of Tunnel-FET
Devices and Circuits for Future Ultra Low Power Applications V Ramgopal Rao, IIT Mumbai, India |
| 11:30-11:45 | Tea Break |
| 11:45-13:35 | Technical
Session IV - Chair: Souvik Mahapatra, IIT Bombay |
| IV-1 |
Surface Acoustic
Wave Device/Sensor Modeling for SPICE Simulation A.B.Bhattacharyya, JIIT Noida, India |
| IV-2 |
Incorporation of
Quantum Mechanical Effects in Compact Models of Bulk MOSFETs Amitava Dasgupta, IIT Chennai, India |
| IV-3 |
RF-SOI modeling
RF front end modules Tamilmani Ethirajan, IBM, India |
| 13:35-14:35 | Lunch |
| 14:35-15:10 | Technical Session IV - Chair: Souvik Mahapatra, IIT Bombay |
| IV-4 |
indDG: A New
Compact Model for Independent Double Gate
Transistor Shantanu Mahapatra, IISc, India |
| 15:10-15:40 | MOS-AK/GSA Poster Session |
| 15:40-16:00 | Tea Break |
| 16:00-18:30 | Technical
Session V - Chair: Ehrenfried Seebacher, AMS, Austria |
| V-1 |
Transitioning
from BSIM4 to BSIM6 Yogesh Chauhan, UC Berkeley, USA |
| V-2 |
Compact modeling
of SOI Drain Extended MOSFET (DEMOS) including High-voltage and
Floating Body Effects M.Jagdesh Kumar, IIT Delhi, India |
| V-3 |
Compact
Modeling: Graphene Transistors Navakanta Bhat, IISC Bangalore, India |
| V-4 |
Performance
Modeling,
Parameter Extraction Technique and Statistical Modeling of Nano-scale
CMOS Transistors for VLSI Circuit Simulation Soumya Pandit, IRPE, Kolkata, India |
| 18:30 onward |
Valedictory Function |
| March 18, 2012: MOS-AK/India Tutorial | |
| T-1 |
CMOS technology and SPICE Models Dr. Narain Arora, Silterra, Malaysia |
| 8.30 | Introductory address Prof. AB Bhattacharyya |
| 9:00-10:30 | MOS Transistors Models (1.5h) Dr. Narain Arora, Silterra, Malaysia Technology trend:
ITRS road map, Cu, OPC, and technology design
Overview of CMOS technology: Evolution of MOS Transistors Sub-100-nm silicon technology and devices for chip design Q & A |
| 11:00-12:30 | SPICE models for advanced CMOS chip design
(1.5h) Samar Saha, SuVolta, Inc., USA Spice MOSFET
models development
New MOS Models: Overview of HiSIM and PSP models Q & A |
| 14:00-17:00 | Interconnect modeling (3.0h) Dr. Narain Arora, Silterra, Malaysia Overview of
interconnect technology and technology trends
Cu interconnect RLC model and extraction Q & A |
| MOS-AK India Committee | |
| Committee: | International Advisory Committee:
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Graphics © 2012 Oliver
Graphics © 2012 Oliver