Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
MOS-AK Workshop
Principles and Practice of the Compact Modeling and its Standardization
Alpes Congres - Alpexpo; Room: Les Bans
Grenoble, Friday, Sept.16 2005

Open Directory
MOS-AK: Enabling Compact Modeling R&D Exchange
Workshop Chair: Dr. W. Grabinski
Technical Program Coordinator: Prof. H. Iwai
  • Morning Session
    • 9:00-12:00 Oral presentations
    • 10:30-11:00 (coffee break)
  • Poster Session
    • 12:00-12:30 Poster presentations
    • 12:30-14:00 (lunch)
  • Afternoon Session
    • 14:00-17:00 Oral presentations
    • 15:30-16:00 (coffee break)
Ansoft Cascade Freescale
Mentor Philips ST
Workshop Program
Display Format: Citation Citation & Abstract
9:00-12:00 Morning Session
  Mixed-Mode Device/Circuit Simulation
Tibor Grasser; Institute for Microelectronics, Technical University Vienna, Austria
  Introduction to the PSP MOSFET model
R. van Langevelde,
G.D.J. Smit, A.J. Scholten, D.B.M. Klaassen; Philips Research Laboratories, Eindhoven, The Netherlands
G. Gildenblat, X. Li, H. Wang and W. Wu; Department of Electrical Engineering, The Pennsylvania State University, University Park, USA
  EKV3.0 - A Design-Oriented Compact MOST Model for Advanced CMOS
Matthias Bucher, Technical University of Crete, Greece
  A Physically Based, Scalable MOS Varactor Model and Extraction Methodology for RF Applications
James Victory1, Zhixin Yan1, Gennady Gildenblat2, Colin McAndrew3, Jie Zheng1; 1 Jazz Semiconductor, Newport Beach, CA 2 Pennsylvania State University, State College, PA 3 Freescale Semiconductor, Tempe, AZ , USA
  Compact Model for Nanoscale MOSFETs in an Intermediate Regime Between Ballistic and Diffusive Transport
Giorgio Mugnaini, Giuseppe Iannaccone Università di Pisa, Italy
12:00-12:30 Poster Session
  RF Modeling of Sub-100 nm CMOS
Satoshi Yoshizaki1, Woei Yuan Chong1, Masayuki Nakagawa1, Yasuo Nara2, Mitsuo Yasuhira2*, Fumio Ohtsuka2, Tsunetoshi Arikado2**, Kunio Nakamura2, Kuniyuki Kakushima1, Kazuo Tsutsui1, Hitoshi Aoki1, and Hiroshi Iwai1
1 Tokyo Institute of Technology, 4259, Nagatsuta-cho, Midoriku, Yokohama, 226-8502, Japan
2 Semiconductor Leading Edge Technologies, Inc. (Selete), Japan
* Current affiliation: Matsushita Electric Industrial Co., Ltd., Japan
** Current affiliation: Tokyo Electron LTD., Japan
  Computer-Controlled System with Programmable Biasing Amplifiers for Low-Frequency Noise Measurements
Guy Piantino, Synergie-Concept, Meylan France
Jan.A. Chroboczek, IMEP/ENSERG, Grenoble, France
  Large Signal Models Validation at Circuit and Device Level by Defining Different Metrics
Monica F. Barciela1, Dominique Schreurs2 and Giorgio Vannini3
1 University of Vigo, Spain, 2 KU Leuven, 3 University of Ferrara, Italy
  Characterization of FD-SOI MOSFETs Based on EKV model
Daniel Tomaszewski1, Denis Flandre2, Piotr Grabiec1, Andrzej Kociubinski1, Christian Renaux2, Krzysztof Kucharski1
1 Institute of Electron Technology, Warszawa, Poland
2 Université Catholique de Louvain, Louvain-la-Neuve, Belgium
  A Closed-form Compact Model for Symmetric Double-Gate (DG) MOSFETs 
Fabien Prégaldiny1, François Krummenacher2, Jean-Michel Sallese2, Birahim Diagne1 and Christophe Lallement1;
1 InESS and 2 EPFL
  Advancements in mm-wave On-Wafer S-Parameter Verification
Larry Dangremond, Cascade Europe
  Analog Simulation and Mixed-Signal System Verification with Mentor Graphics tools: Eldo, Eldo RF and ADVanceMS
Philippe Raynaud, Mentor Graphics, France
  Nexxim®: Ansoft's New State-of-the-Art Circuit Simulator for RF, Analog and Mixed-Signal Design
Alain Michel, Ansoft Europe
  Next Generation MOS Modeling in IC-CAP
Thomas Gneiting, AdMOS, Germany
Franz Sischka, Agilent Technologies, Europe
  A New Analytical Quasi Ballistic Model for Nano MOSFET
Emmanuel Fuchs and André Juge; STMicroelectronics, Crolles, France
12:30-14:00 Lunch
14:00-17:00 Afternoon Session
  Challenges and Strategies for the SPICE Model Extraction and Simulation of the PD-SOI Technology
Jung-Suk Goo; Advanced Micro Devices, Sunnyvale, CA, USA
  Asymmetrical Double Gate (DG) MOSFET Compact Modeling
O. Rozeau, M. Reyboz, T. Poiroux, P. Martin; LETI-CEA, Grenoble, France
  Circuit Modeling of Non-Volatile Memory Devices
Mike Sadd, Rajesh Rao and Ramachandran Muralidhar, Reiner Thoma; Freescale Semiconductor, Austin, USA
  Analog/HV Characterisation for 0.35µm High Voltage Technology
Ehrenfried Seebacher; austriamicrosystems AG, Premstätten, Austria
  Table Based Models
Victor Bourenkov1 and Kevin G. Mccarthy2; 1 Tyndall Nat. Inst. 2 UCC, Ireland
17:00 End of the workshop
update 22-Sept-05
Contents subject to change ©2005 All rights reserved. WG