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Arbeitskreis Modellierung von Systemen und Parameterextraktion Modeling of Systems and Parameter Extraction Working Group MOS-AK Workshop Principles and Practice of the Compact Modeling and its Standardization Alpes Congres - Alpexpo; Room: Les Bans Grenoble, Friday, Sept.16 2005 |
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Open
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Mission |
Committee |
MOS-AK: Enabling
Compact Modeling R&D Exchange
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Workshop
Chair: Dr. W. Grabinski
Technical Program Coordinator: Prof. H. Iwai |
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| 9:00-12:00 | Morning Session | |||||
| Mixed-Mode
Device/Circuit Simulation Tibor Grasser; Institute for Microelectronics, Technical University Vienna, Austria |
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| Introduction
to the PSP MOSFET model R. van Langevelde, G.D.J. Smit, A.J. Scholten, D.B.M. Klaassen; Philips Research Laboratories, Eindhoven, The Netherlands G. Gildenblat, X. Li, H. Wang and W. Wu; Department of Electrical Engineering, The Pennsylvania State University, University Park, USA |
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| EKV3.0 -
A Design-Oriented Compact MOST Model for Advanced CMOS Matthias Bucher, Technical University of Crete, Greece |
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A Physically Based, Scalable MOS Varactor Model and Extraction
Methodology for RF Applications James Victory1, Zhixin Yan1, Gennady Gildenblat2, Colin McAndrew3, Jie Zheng1; 1 Jazz Semiconductor, Newport Beach, CA 2 Pennsylvania State University, State College, PA 3 Freescale Semiconductor, Tempe, AZ , USA |
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| Compact
Model for Nanoscale MOSFETs in an Intermediate Regime Between Ballistic
and Diffusive Transport Giorgio Mugnaini, Giuseppe Iannaccone Università di Pisa, Italy |
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| 12:00-12:30 | Poster Session | |||||
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RF Modeling of Sub-100 nm CMOS Satoshi Yoshizaki1, Woei Yuan Chong1, Masayuki Nakagawa1, Yasuo Nara2, Mitsuo Yasuhira2*, Fumio Ohtsuka2, Tsunetoshi Arikado2**, Kunio Nakamura2, Kuniyuki Kakushima1, Kazuo Tsutsui1, Hitoshi Aoki1, and Hiroshi Iwai1 1 Tokyo Institute of Technology, 4259, Nagatsuta-cho, Midoriku, Yokohama, 226-8502, Japan 2 Semiconductor Leading Edge Technologies, Inc. (Selete), Japan * Current affiliation: Matsushita Electric Industrial Co., Ltd., Japan ** Current affiliation: Tokyo Electron LTD., Japan |
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Computer-Controlled System with Programmable Biasing Amplifiers for
Low-Frequency Noise Measurements
Guy Piantino, Synergie-Concept, Meylan France Jan.A. Chroboczek, IMEP/ENSERG, Grenoble, France |
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Large Signal Models Validation at Circuit and Device Level by Defining
Different Metrics Monica F. Barciela1, Dominique Schreurs2 and Giorgio Vannini3 1 University of Vigo, Spain, 2 KU Leuven, 3 University of Ferrara, Italy |
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Characterization of FD-SOI MOSFETs Based on EKV model Daniel Tomaszewski1, Denis Flandre2, Piotr Grabiec1, Andrzej Kociubinski1, Christian Renaux2, Krzysztof Kucharski1 1 Institute of Electron Technology, Warszawa, Poland 2 Université Catholique de Louvain, Louvain-la-Neuve, Belgium |
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| A Closed-form
Compact Model for Symmetric Double-Gate (DG) MOSFETs Fabien Prégaldiny1, François Krummenacher2, Jean-Michel Sallese2, Birahim Diagne1 and Christophe Lallement1; 1 InESS and 2 EPFL |
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Advancements in mm-wave On-Wafer S-Parameter Verification
Larry Dangremond, Cascade Europe |
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Analog Simulation and Mixed-Signal System Verification with Mentor
Graphics tools: Eldo, Eldo RF and ADVanceMS Philippe Raynaud, Mentor Graphics, France |
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Nexxim®: Ansoft's New State-of-the-Art Circuit Simulator for RF, Analog
and Mixed-Signal Design
Alain Michel, Ansoft Europe |
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Next Generation MOS Modeling in IC-CAP
Thomas Gneiting, AdMOS, Germany Franz Sischka, Agilent Technologies, Europe |
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A New Analytical Quasi Ballistic Model for Nano MOSFET
Emmanuel Fuchs and André Juge; STMicroelectronics, Crolles, France |
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| 12:30-14:00 | Lunch | |||||
| 14:00-17:00 | Afternoon Session | |||||
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Challenges and Strategies for the SPICE Model Extraction and Simulation
of the PD-SOI Technology Jung-Suk Goo; Advanced Micro Devices, Sunnyvale, CA, USA |
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| Asymmetrical
Double Gate (DG) MOSFET Compact Modeling O. Rozeau, M. Reyboz, T. Poiroux, P. Martin; LETI-CEA, Grenoble, France |
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| Circuit
Modeling of Non-Volatile Memory Devices Mike Sadd, Rajesh Rao and Ramachandran Muralidhar, Reiner Thoma; Freescale Semiconductor, Austin, USA |
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| Analog/HV
Characterisation for 0.35µm High Voltage Technology Ehrenfried Seebacher; austriamicrosystems AG, Premstätten, Austria |
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| Table
Based Models Victor Bourenkov1 and Kevin G. Mccarthy2; 1 Tyndall Nat. Inst. 2 UCC, Ireland |
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| 17:00 | End of the workshop | |||||
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