S. Cristoloveanu:
Typical mechanisms in advanced SOI MOSFETs and challenging issues for compact modeling
  abstract; slides
 

Y.V. Ponomarev:
Role of Compact Modeling in Scaled CMOS Technologies Development

The necessity to aggressively scale CMOS to sustain the historical trend of performance improvement with every generation calls for inevitable introduction of new materials (high-k gate dielectrics, metal gate electrodes, mobility-enhancing materials in the channel) and alternative transistor architectures, such as FD-SOI and Multi-Gate transistors (FinFET, Double Gate, SON, etc.). However, this will have significant consequences to the operation of all parts of the IC, which might be either beneficial or detrimental, depending on the application block. We will review the effects caused by the introduction of new gate stack materials and transistor architectures, with special emphasis on devices in the analogue/RF parts of the circuitry. We will show that early feedback loop provided by Compact Modeling between technology development on one side and application domains on the other is of vital importance to ensure future SOC success.
 

L.Lemaitre:
Software Tools for CM Standardization

In this talk two open-source projects - ADMS and ZSPICE - contributing to the standardization effort for compact modeling are presented. ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. ZSPICE is a simple highly reconfigurable spice simulator. Its device library is automatically generated using ADMS.
Please refer also to: http://sourceforge.net/projects/mot-adms http://sourceforge.net/projects/mot-zspice/
 

G. Wachutka:
Coloured Kirchhoffian Networks for Multi-Energy and Multi-Signal Domain Microsystem Models

Currently strong efforts are being made to build simulation platforms for the predictive simulation of micro- and nanomechatronical devices and systems (MEMS/NEMS), as this constitutes the cost-effective and time-saving alternative to the traditional experimental approach. Already today the rapid progress in microsystems technology is strongly supported by MEMS-specific modeling methodologies and dedicated simulation tools constituting a "virtual laboratory" on the computer, which enables the visualization and detailed analysis of the operating behavior of single microdevices as well as their collaborative function in a microsystem.
In this context, one of the most important aspects is the consistent treatment of coupled fields and coupled energy and signal domains required for deriving macromodels of microsystems from the continuous field level. To this end, we propose mixed-level methods for setting up physically-based consistent full system models for the effort-economizing and yet accurate numerical simulation of micro- and nanomechatronical components and systems. The key to a full system description is a uniform treatment of all kinds of energy and signal flows together with their desired or parasitic interactions in terms of coloured Kirchhoffian networks and their representation in a hardware description language such as VHDL-AMS or Verilog-A.

S. Cristoloveanu:
Typical mechanisms in advanced SOI MOSFETs and challenging issues for compact modeling.

The frontiers of the conventional CMOS era become extremely visible. In particular, the scaling of bulk silicon transistors will stop far before reaching the 10-20 nm channel length barrier. This explains the renewed interest in Silicon On Insulator (SOI), which is becoming a mainstream technology, adopted by several leading companies. The availability of compact models is a necessary condition for the key advantages of SOI devices to materialize in terms of enhanced performance and extended potential for scalability. The aim of this talk is two-fold: (i) present typical mechanisms that appear in state-of-the-art SOI MOSFETs, and (ii) propose appropriate physics-based models to be included in circuit simulators. Several issues will be addressed, including:
Gate tunneling currents and floating-body effects. SOI transistors with ultra-thin oxide can have the body charged not only by impact ionization but also by gate tunneling. This leads to significant changes in transconductance, noise, and transient effects. Different models apply to partially and fully depleted SOI MOSFETs.
Short-channel effects. The major effect, due to the fringing fields, is the drain-induced virtual substrate biasing.
Narrow-channel effects. According to the techniques used for lateral isolation, various problems may arise: inhomogeneity in carrier concentration, mobility and lifetime, causing an overall decrease of floating-body effects. Ultra-thin film effects. Giant coupling effects between the two channels are observed in 10-nm-thick SOI
transistors. If the buried oxide is equally thin, substrate depletion underneath the BOX needs to be accounted for.
Self-heating. There are technological solutions to limit self-heating and mobility degradation. However, a trade-off between thermal and electrical properties becomes necessary which implies coupled models. Transport and mobility properties. The body of advanced SOI transistors can in principle be undoped. However, the relation between mobility and film thickness is still controversial.
Double-gate operation. There is no doubt that ultimate MOSFET scaling, beyond 10-20nm channel length, will require ultra-thin SOI transistors with double-gate architecture. Typical issues are related to volume inversion, quantum confinement, and presumable enhancement in carrier mobility.
Multiple-gate transistors. Tri-gate and four-gate transistors have recently been investigated. Special models, including the length-doping transformation, are needed to describe the co-operative action of the various gates.

 

C.Enz, M. Bucher, F. Krummenacher, J.-M. Sallese, A.-S. Porret, C. Lallement:
Charge-Based MOS Transistor Modeling in EKV 3.0

An overview on key concepts used in the charge-based MOS transistor modeling in the EKV model is presented: ideal charges model for static, quasi-static dynamic and non-quasistatic (NQS) effects including NQS noise.The model covers all operating regions from weak to moderate and strong inversion and addresses symmetric forward and reverse operation.The new version 3.0 of the EKV MOSFET model introduces extensions to the ideal model to account for high-field and short-channel effects in advanced CMOS technology. Among the extensions considered are polydepletion and quantum effects, as well as modeling of short-channel effects including bias-dependent overlap charge/capacitances. The charges/transcapacitances model shows excellent behavior in terms of symmetry aspects and asymptotic behavior, while requiring a minimum number of model parameters. Model evaluations in advanced CMOSprocesses are presented.

 

T. Gneiting:
A Parameter Extraction Framework for Next Generation MOS Models

As CMOS technology is scaling towards the nanometer regime, a new generation of appropriate MOS simulation models is available for the design community. While the last decade has been dominated by Berkeley's BSIM3 and BSIM4 models, new concepts like the HiSIM1 or the Philips MM11 model are accepted more and more in the semiconductor industry. This poster presents a parameter extraction framework which can generate those different model types from one unified set of measured data. All important steps starting from the definition of the test patterns through measurement, data handling, parameter extraction and quality assurance are discussed.

 

V.I. Hahanov, V.I. Obrizan, O.V. Melnikova, Gowher Malik:
Fast Fault Simulation Method for Digital Systems

Fast fault simulation method oriented on processing of complex digital devices containing hundreds of thousand equivalent gates is offered. The method is oriented on considerable (dozens of times) fault simulation and test generation time decrease. Such results can be achieved due to application of new structural and logical analysis technologies, object reconfiguration during the processing. Unit under test - is digital system, represented in form of Boolean equations, described on VHDL language. New methods of structural analysis based on searching reconvergent fan-out and reconfiguration of circuit for purpose of fault simulation speed-up are offered. The practical use of new technology on hundreds of combinational and sequential circuits gave good results in comparison with deductive and parallel fault simulation methods.

N. Hefyene, C. Anghel and A. Ionescu:
HV MOSFET modeling with EKV

HV Lateral MOSFETs are extremely interesting for automotive and RF applications. Presently, HV MOSFETs are usually integrated together with low voltage modules, which explain the strong demand for accurate models dedicated to these devices.
Particular challenges for advanced LDMOS modeling, such as the bias-dependent drift series resistance (DC) and the gate-to-drain capacitance (AC), are addressed in this work. We report on a modeling strategy for LDMOS transistors that exploit the partition of the device into: (i) the intrinsic channel region, modeled by a low-voltage EKV model and (ii) the drift region, the resistance and charge of which are calculated with a specific analytical model. We demonstrate that, due to its physical foundation, reduced number of parameters and unrivalled continuity, EKV is the best choice as core intrinsic channel model for such modeling approach. We also report on the model parameter extraction and on the resulting accuracy.

 

B. Iñiguez, J. Østhaug and T. A. Fjeldly:
Analytical 2D Modeling of Sub-100 nm Mosfets Using Conformal Mapping Techniques

We present a closed-form 2D modeling technique of sub-100 nm MOSFETs. This technique is based on conformal mapping where the 2D Poisson's equation in the depletion regions is separated into a 1D long-channel case and a 2D Laplace equation. The 1D solution defines the boundary potential values for the Laplacian, which in turn provides a 2D correction of the channel potential. This approach can be applied to all MOSFET structures: from classical bulk MOSFETs to single- and double gate SOI MOSFETs. We show results obtained for several MOS structures, with channel lengths down to the sub-100 nm range. Using a minimal parameter set, the present modeling reproduces both qualitatively and quantitatively the experimental data obtained for such devices, without the need to introduce any empirical or semi-empirical equations.
 

P. Raynaud:
Mixed-Language Simulation for Analog/Mixed-Signal Design

Analog/mixed-signal SoC designs combine analog and digital content more tightly than ever before. They increasingly depend on integrated analog blocks such as A/D and D/A converters, phase-locked loops, and adaptive filters. This increased level of integration puts tremendous pressure on designers. Traditional design tool flows force designers to develop analog and digital subsystems in isolation, delaying the integration of these components until IC layout, and the testing until after fabrication. Because of this, AMS SoC design has become a slow, expensive and error-prone process. AMS SoC designers need the same kind of tool integration that digital designers already enjoy - hardware description languages (HDLs) and behavioral models that automate the design process. This is the level of automation provided by Mentor's advanced AMS simulation products.
 

B. New, C. Woodin, T. Alam, G. Fisher:
A Device Measurement Package for Characterization and Modeling

Presentation of a new software package for performing RF and DC measurements of devices for the purpose of characterization and modeling. The modular software package performs measurements of S Parameters, IV/CV curves, controls DC Bias conditions and wafer stepping. By exporting measurement data in MDM format, the software allows IC-CAP to be used for model extraction. Data is managed with a project/device data-flow model so that results can be easily shared between multiple users. The instrument/office edition architecture allows users to setup test projects and review test results from their desktops; this means that the measurement equipment is fully utilized for taking measurements and ICCAP can be utilized exclusively for modeling and parameter extraction. The report tool lets users show measurement data in a variety of formats, allows data to be compared from different tests and will show wafer map binning results.
 

F. Sischka:
IC-CAP 2003 Features

After the introduction of IC-CAP 2002, which migrated IC-CAP to the PC platform, the new release 2003 offers the following features:

- new Agilent DC Analyzer E2070A driver
- new Agilent PNA network analyzers driver (PNA series)
- new graphics
- new optimizers
- new PlotOptimizer feature for easier curve fitting (demo of prototype)
- improved interface to Spectre, new Spectre parser
- BSIM-SOI toolkit

A demo of IC-CAP 2003 will be available during the workshop meeting.

One of the common complaints from the RF circuit designer is the accuracy of RF device model and insufficient device library provide by foundries. This is obviously seen in the case of RF active devices and RF inductors in the design kit provide by the foundries. This bottleneck has restricted the freedom in circuit implementation and provides no room for circuit fine tuning. Advanced RFIC, one of the leading RF device modeling labs in Asia, has realized these problem faced by the RF designers. It develops scalable RF device model and further implement it into the common EDA tools. The result is faster time to market with the fewer MPW run and shorten the design cycle of developing an IC. Advanced RFIC equipped with the advanced probe station from Cacade Microtech S300 (12”) and test instruments from Agilent , ATN and Celestry (Cadence). We provide fast and accurate RF CMOS, EKV and Mextram model extraction services and development of design kit with aim to shorten cycle and improvement of design accuracy. For detail information, please refer to www.arfic.com

A. J. Scholten, R. van Langevelde, L. F. Tiemeijer, R. J. Havens, and D.B.M. Klaassen:
RF Applications of MOS Model 11

As modern CMOS is rapidly progressing towards sub-100 nm dimensions, RF performance of MOS devices is improving strongly. Therefore, CMOS has become a viable option for RF applications. To exploit the RF capabilities of CMOS, compact models for circuit simulation are required that describe all relevant quantitiesRF designers are interested in: not only currents and charges, but also noise figure, power gain, impedance levels, and harmonic distortion.In this presentation several of these issues will be addressed using Philips' compact MOS model, MOS Model 11 (MM11) and its RF extensions.MM11 has been developed in order to accurately describethe MOSFET currents as well as their higher-order derivatives(up to 3rd order) with respect to all terminal voltages. MM11 is based on a continuous descriptionof the surface potential throughout all operating regimes, including theincreasingly important moderate inversion regime.
While MM11 gives an excellent description of thir-order harmonic dostortion, the RF extension has to be used in order to obtain adequate modelling of quantities affected by non-quasi static effects, e.g. impedance levels and power gain.

 

M. Sadd and R. Muralidhar:
Compact Modeling of Non-volatile Memory Devices

Memory devices exploit the natural hysteresis of any of several physical processes to store information. These process often operate under conditions that the very different from logic CMOS-or would actually represent a failure mode for logic transistors. Modeling these processes therefore involves a set of challenges apart from modeling analog or logic devices. We will illustrate some of these issues by concentrating on charge storage non-volatile memories (NVM). The first step in modeling these devices is extraction of the underlying FET parameters and coupling capacitances. This procedure is well understood. Accurately modeling the program and erase operations is somewhat more difficult, however. Finally, we introduce the challenges posed in modeling charge trapping devices, such as SONOS and the nano-crystal memory, which are leading candidates for scaling silicon NVM past 0.1 m.

 

A. Laigle, F. Martinez, A. Hoffmann and M. Valenza:
MOSFETs Flicker Noise Modelling For Circuit Simulation

To improve performance at increasing operational frequencies, dimensions, especially channel length in MOSFETs, are now scaled down to deep submicron values. The low frequency noise is becoming a major concern for network performance limitation and needs to be accounted in the design of analog circuits. Therefore, for analog simulation, accurate noise models are required in order to predict its impact on circuit behaviour. Ideally, a single model, based on physical principles, should describe the low frequency noise in both n-type and p-type MOSFETs and in all accessible drain and gate biases. Actually only BSIM allows this.
In the first part of this tutorial an overview of Low Frequency Noise Measurement techniques using commercial instrumentation is given. Procedure to minimise the background noise of the experimental set up is presented.
 

G. Rappitsch
Statistical Spice Modeling for Analog Circuit Design

Design for manufacturability strongly relies on the accurate compact modeling of process variation. Different methods for the development of statistical SPICE models are presented and their usefulness with respect to analog design applications is discussed. The basis of all presented methods is a physical and scalable compact model allowing for a direct correlation of model parameters to process- or production control parameters. As a standard approach the generation of best case/worst case corner models is described where certain parameters are combined to maximize a single device performance (e.g. speed or power). Those models allow the designers to consider the effect of process variation and to design their circuits to be tolerant of them. A problem is the generation of pessimistic corner models forcing the designer to meet artificial worst case limits.
A more sophisticated method is the generation of parametric Monte Carlo models. Certain device parameters are modelled to have a statistical distribution imitating the random variation of process parameters. By taking into account crucial device correlations and local mismatch effects according to the Pelgrom law a very realistic picture of the performance spread is obtained during Monte Carlo simulation of analog circuits.
A further method is presented enabling the generation of process corner models by means of multivariate statistical methods. Corner wafers are determined from production control parameters using a location depth algorithm and the selected corner vectors are transformed to SPICE parameters applying a linear mapping. The obtained simulation setup preserves the original correlation structure and allows a realistic checking of circuit robustness with a moderate number of corner simulations.
The practical implementation of statistical models for foundry process design kits is demonstrated and the methods are compared using analog benchmark circuits.