Arbeitskreis MOS-Modelle und Parameterextraktion MOS Modeling and Parameter Extraction Working Group MOS-AK/ESSDERC/ESSCIRC Workshop Friday, 19 September 2008 at Edinburgh International Conference Centre (EICC)

Agenda: Friday, 19 September 2008 at Edinburgh International Conference Centre (EICC)
Morning Session 9:00-11:30 Oral presentations 10:00-10:30 (coffee break)	Poster Session 11:30-12:00 Posters 12:00-13:00 (lunch)	Afternoon Session 13:00-16:00 Oral presentations 14:30-15:00 (coffee break)

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Poster Session Program

Display Format: Citation Citation & Abstract
11:30-12:00	Poster Session Chair: W.Grabinski, GMC
	Simulation of CMOS Inverters Based on the Novel Surrounding Gate Transistors. A Verilog-A implementation A. Roldan, J.B. Roldan, F. Gamiz; Universidad de Granada Abstract:  The main features of CMOS inverters based on the novel surrounding gate transistors (SGT) have been analyzed. A Verilog-A compact model for the SGT has been implemented to study both basic analog and digital circuits. The initial classical drain current model has been enhanced to account for quantum effects. Both the electron and hole layers are known to be highly confined in these structures due to structural as well as electrical confinement. The influence of confinement effects in several circuits based on these quantum nanowires are characterized in depth. In particular, CMOS inverter gate delays, CMOS inverter ring oscillator frequencies, etc., have been obtained in order explore the relations between the most representative technological parameters of the transistors and the inverters performance.
	Xsim: Unification of MOSFET Compact Models with the Unified Regional Modeling Approach Guojun Zhu, Guan Huei See, Shihuan Lin, Chengqing Wei, Junbin Zhang, Zuhui Chen, Ramachandran Selvakumar, and Xing Zhou; Nanyang Technological University, Abstract:  This poster presents the motivation and philosophy behind the development of a compact model (Xsim) for unification of MOSFET models with the unified regional modeling (URM) approach. It is based on unified regional surface potential solutions for generic double-gate (including SOI and nanowire) MOSFETs with common/independent-gate biasing and with/without body contact. The DC/AC model is physically scalable in geometry/bias as well as in body thickness and doping, encompassing partial/full-depletion and volume inversion. New paradigm shift in ground-referencing and source/drain-by-label provides complete Gummel symmetry while allowing physical modeling of asymmetric devices, which also provides easy extension to include contact effects for modeling doped as well as Schottky-barrier source/drain. The core model is directed towards modeling emerging devices and technologies in one unified framework without duplicating efforts, which also provides seamless transitions among various device structures and operations, with selectable accuracy for simulation and verification of future-generation ULSI circuits.
	Ngspice Batch and Distributed Analysis and Data Postprocessing Alberto Lucchini, Paolo Nenzi, Francesco Nizzi, Mauro Olivieri and Lionel Sainte Cluque; Uni Roma "La Sapienza", NGSpice SourceForge. Abstract:  Tclspice is the binding of spice simulator in a shared library. Spice commands can be called in a TCL/TK shell or script. It started as an independent project by Stefan Jones and now is chaired by Lionel Sainte Cluque with the aim of integrate it with ngspice. Tclspice has many advantages: * Electronic designers often know TCL: it is used in many tools. For example ngspice can do post synthesis simulation of digital ASICs using the TCL shell of the digital tool. * The TCL scripts are portable on any OS tclspice can be compiled on: For example a Monte Carlo simulator written for tclspice can be used on any computer tclspice is installed on. * Tclspice addresses problems regular spice does not: simulate a circuit and export data in an OpenOffice spreadsheet. Optimize component values, or build a web server on which the visitor can upload a netlist and get an HTML page with simulation output.
	Evaluation of the EKV3 Compact Model for Low Temperature Analog Circuit Simulation Patrick Martin; CEA-LETI Minatec, Raphael Fascio; CEA-LETI Minatec, Gerard Ghibaudo; IMEP Minatec and Matthias Bucher; TUC Abstract:  An evaluation of the EKV3 compact model for low temperature (77K - 200K) analog circuit simulation is presented. This evaluation is performed on a dual gate 0.18µm CMOS process with 1.8V and 3.3V transistors. We show that standard effects, such as RSCE and INWE, are well modeled by EKV3 when using adapted temperature laws. Some specific effects observed at low temperature are also described. For example, we observe a peak in the transconductance in some lightly doped NMOSFETs. TCAD Poisson-Schrödinger simulations with Atlas (Silvaco) show that there is a strong correlation between the Gm peak and the change of occupancy of the first energy subband with the gate voltage. Freeze-out effects are also observed in LDD zones of 3.3V MOSFETs. A Verilog-A modified version of EKV3 allows predicting the freeze-out effects and impurity ionization in LDD zones. In conclusion, this evaluation shows that EKV3 is a good candidate for analog circuit simulation at low temperature, but should be improved for accurate modeling in the temperature range 77K - 300K. Some quantum effects, such as subband filling, are not yet modeled.
	Lateral PNP Transistor Modeling with SPICE Models Vaclav Panko; OnSemi Abstract:  Adapted models of vertical NPN transistor are still mostly used for modeling the lateral PNP transistors. It causes inaccurate modeling because the behavior of laterally arranged PN junctions is different than vertically arranged PN junction. This presentation deals with the comparison of the several possible models of a lateral PNP transistor with the MODELLA model developed by Philips company. Differences among models are identified in DC/AC modes. A special attention is paid to the saturation region and models capabilities to describe scattering parameters (S parameters).
	An Integrated Approach for More Accurate, Wafer-Level Parameter Measurements Stojan Kanev, Andrej Rumiantsev, Joshua Preston SUSS MicroTec
	Verilog-A Model Support from Tanner EDA - Bringing benefits to developer and user alike Paul Double; EDA Solutions Abstract:  A new generation of Verilog-A tools is providing compact, accurate models that can dramatically speed up the simulation of analogue designs and opens up the opportunity for top down design methodologies. This language is being used to develop and implement compact models of analogue components. These replace the built in models in the Spice simulator to provide an accurate but significantly faster simulation. Simulation times are typically 10 times faster than the models written in C, and the cost of developing the Verilog-A models is similarly one tenth that of developing the same model in C. Furthermore, the Verilog-A models are also easier to modify for different transistor or semiconductor manufacturing processes for different requirements such as wear modelling or self healing, where there may be different process parameters. Tanner EDA has integrated the compiler and simulator-specific run time environment (RTE) from Tiburon Design Automation to create a tool called HiPer Simulation. This allows Tanner's T-Spice Pro simulator to take a model written in Verilog-A and automatically generate a version in C. This C model is then compiled to run in the simulator. The tool can read existing analogue netlist formats such as HSPICE and P-Spice directly so that existing models can be used alongside the Verilog-A models, and includes a Simulation Manager and device modelling functions. T-Spice Pro already offers support for Penn State Philips Model (PSP), BSIM3.3, BSIM4.5, BSIM SOI, EKV, MOS11, MOS20, VBIC and MEXTRAM models. Custom models can also be created using algebraic expressions for voltage and current controlled sources, data from external tables, or the C programming language. Tanner ships a wide variety of tested, common transistor models in Verilog-A format, where the parameters are easy to modify and use in the T-Spice simulator. This is being used particularly in TFT screen designs and in micromachined MEMS designs, working alongside the S-Edit and L-Edit tools.
	PQA – Variability-Aware Verification Platform for the sub-45nm PDK Tim K. Smith, Xisheng Zhang, Albert. Li, James Ashforth-Pook; Accelicon Abstract:  Leading foundries provide variability-aware SPICE models and parasitic extraction decks modeling DFM effects at 45nm and below. Proper model-based analysis of design layout structures is important to predicting design margins influenced by process/design variability. Managing margins allow for a more compact, better performing, design. PQA automates the SPICE analysis of DFM effects, provided from foundry models, of test layout structures.
	Compact Modeling of SiON MOST Devices Jakub Jasinski, Grzegorz Głuszko, Lidia Lukasiak, Andrzej Jakubowski; Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Wladyslaw Grabinski;GMC, Daniel Tomaszewski; ITE Warsaw Abstract:  One of the most critical issues of the miniaturization of MOS devices to sub-100 nm dimensions is the reduction of gate-dielectric thickness, and the resulting increase of gate leakage current. The best way to increase the physical thickness of the gate dielectric (and reduce gate current) without detrimental influence on gate control over the channel is to use a high-k material. While the dielectric constant of SiON is not very high, the quality of its interface to silicon is much better than that of many high-k materials, which is why it is often used as a part of a dual gate-dielectric. Compact modelling is indispensable for design of circuits with such devices, therefore in this work extensive electrical characterization of MOSFETs with 1.2 nm SiON gate dielectric and poly-Si gate electrode is used to determine the parameters of the EKV model, taking into account other engineering issues (e.g. halo implants).
	RF – MOS Modelling Sebastian Schmidt, X-FAB, Erfurt Abstract:  Mos transistor devices capable for RF simulation need some additional layout considerations as well as modelling precautions. This work shows a simple way of constructing a model using the standard BSIM3v3.42 mos model. The additional model circuitry resembles the BSIM4 philosophy regarding substrate circuitry. However, the geometrical scaling in a limited range is the focus of this modelling work. Thus a set of scaling rules for both, gate resistance and substrate resistance network, was established. A set of devices was investigated, ranging from the smallest consisting of two gate fingers at W=1.6µm to the largest having ten fingers at the maximum width of 8.0µm. The scaling of the S- parameter simulation with width is demonstrated against measurement. This is similar to the scaling with number of fingers.
	Effect of a Local Ground and Probe Radiation on the Microwave Characterization of Integrated Inductors Gavin Fisher, Cascade Microtech Europe Abstract:  Cascade Microtech has recently been making advances in the field of Rf measurement technology. This presentation highlights three examples: * A collaborative paper between TU Delft and Cascade - Effect of a Local Ground and Probe Radiation on the Microwave Characterization of Integrated inductors. * The introduction of the new Unity probe, that allows multifunction with multiple resonance free DC bias or multiple Rf test up to 20 GHz (8 channels) or combinations of both. * Development of the Wincal XE measurement and calibration software has been extended to incorporate the multi-line style TRL algorithms developed by NIST. Wincal XE now allows automated calibration with the use of Cascades motorized ms1 positioners to leverage the benefits of this calibration technique.
12:00	End of the MOS-AK Poster's Session
	MOS-AK presentations recommended for further publication

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No.#9849

update: 30-Sept-08 (rev. b)

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