MOS-AK at ICC Edinburgh

Abstract:
Thanks to the evolution of fine fabrication technologies of ultra-deep submicron CMOS process, it has been realized the RF performance of MOSFET such as cutoff frequency exceeded 200GHz, which has already caught up with that of an advanced SiGe HBTs. This enables Si industry to provide market with high-speed purely CMOS SoC products. By silicon foundries' standpoint, providing customers with an accurate compact model is very important, but in most cases, it is not an easy task. Because compact model should incorporate more numbers of small-size effects for DC scaling and introduce high-frequency distribution effects such as NQS (Non Quasi Static) effects for RF scaling including noises. In his presentation, following two key-features will be discussed by taking a case of TOSHIBA's 65nm RF-CMOS PDKs' (process design kits); (1) A creation of a scalable model card for components (MOSFETs and passive devices) and (2) review of modeling difficulties by the use of current compact modeling technologies. It will be shown that precise modeling of gate resistance and its scalability is a key for the creation of scalable RF-MOSFET model.

Abstract:
The EKV3 model for high-frequency application is described. The EKV3 model covers scalable mulit-finger RF transistor modelling, including layout-dependence. Different setups accounting for substrate and gate parasitics at high-frequency are available to the designer. Also, non-quasi static effects are accounted for by using channel segmentation. The different choices are discussed and compared, and the RF parameter extraction is outlined. RF modelling examples cover the different scaling scenarios for various technologies from 180nm to 90nm CMOS.

Abstract:
High-voltage (HV) MOS transistors can be used in a wide variety of applications like power management, motor control, print drivers, DC/DC converters, switched power supplies and LCD drivers. Though BSIM based subcircuits can be used for all kinds of HV devices including parasitic effects the model is unphysical and the derivatives are inaccurate. The urgent need for an industrial standard compact model obliged the Compact Model Council (CMC) to start standardization in 2006. The CMC has been intensively evaluating three potential candidates: The HiSIM_HV model developed at Hiroshima University, the MM20 model of the Technical University of Eindhoven and the EKV-HV model of EPFL, Lausanne. The HiSIM_HV and EKV-HV provide compact model solution describing the behavior of all the important regions: channel, accumulation and drift region. The MM20 model needs additional drift region model. Geometry scaling effects are not fully addressed in each model. Meanwhile, HiSIM_HV has been selected for standardization and is already available in many simulators and parameter extraction tools. In this paper we will present benchmark results of the proposed models with respect to I-V, C-V, 1/f behavior versus measurements and gummel test results in conjunction with the AMS BSIM3 based subcircuit model.

Abstract:
We review compact modelling techniques used so far for thin-film SOI MOSFETs. We explain the physical basis of the main modelling principles used to develop compact models of different types of thin-film SOI MOSFETs and we critically discuss the approximations used. The devices targeted are the Single-Gate Fully-Depleted SOI MOSFET, the Single-Gate Accumulation-Mode SOI MOSFET, The Single-Gate Ultrathin Body (UTB) SOI MOSFETs, and the main types of Multiple-Gate MOSFETs, such as Gate All Around (GAA), symmetrical Double Gate (DG) MOSFETs and FinFETs We address the electrostatic modelling, the transport modelling, and the development of models for the drain current, charges and small- and large-signal parameters. The accuracy of the main existing models is analyzed. The main direct parameter extraction techniques are also shown. We also explain the techniques by means of which some of these models have been extended to the high frequency and noise analysis. Finally, we discuss the challenges these models face with in order to be used below the 32 nm technological node.

Abstract:
This presentation will discuss modern approaches to modelling and performance optimisation of mixed-technology energy harvaster systems that comprise electrical and non-electrical parts. An electromagnetic vibration-base energy harvester with associated analogue electronics is used as a case study to illustrate an automated design flow where energy-harvester components are optimised and synthesised for best performance. It will be shown how a genetic algorithm can be efficiently implemented in an HDL testbench to optimise performance and automatically select the best voltage booster architecture and calculate the micro-generator design parameters.

Abstract:
This talk will present the charge-based model that covers the static and dynamic operation of the MOS transistor from weak to strong inversion. The model includes the dc drain current, the small-signal equivalent circuit and the noise. All the parameters such as the dc drain current, the transconductances, capacitances, transcapaciatnces, admittances, transadmittances and the noise can be expressed in terms of the inversion charges qs and qd evaluated at the source and drain, respectively. The charge-based model establishes a link between the inversion charges qs and qd and the transconductances from the source and the drain as well as the current and the inversion factor. It allows for a simple physical expression of the Gm/ID characteristic which is often used for analog circuit optimization.

Abstract:
The three design choices of drain current, channel width, and channel length required for every MOS transistor greatly complicate analog CMOS design, but provide significant opportunities to optimize circuit performance. Use of the inversion coefficient, which is a numerical measure of MOS inversion, enables design freely in weak, moderate, and strong inversion and facilitates optimum design. Here, channel width required for layout is easily found and implicitly considered in performance expressions. This tutorial describes hand expressions and measured data illustrating tradeoffs in MOS device performance, including effective gate-source bias and drain-source saturation voltages, transconductance efficiency, normalized drain-source conductance, capacitances, gain and bandwidth measures, thermal and flicker noise, and mismatch. A simple spreadsheet tool is then used to predict MOS device performance and map this into complete circuit performance. Tradeoffs and optimization of performance are illustrated by the design of three, 0.18um CMOS operational transconductance amplifiers optimized for DC, balanced, and AC performance. Measured performance shows significant tradeoffs in voltage gain, output resistance, transconductance bandwidth, input-referred flicker noise and offset voltage, and layout area. Because of the technology normalization present when using the inversion coefficient, the design optimization methods presented are readily extended to smaller geometry processes. The methods provide design intuition leading towards optimum design, while minimizing trial-and-error simulations.

Agenda: Friday, 19 September 2008 at Edinburgh International Conference Centre (EICC)
Morning Session 9:00-11:30 Oral presentations 10:00-10:30 (coffee break)	Poster Session 11:30-12:00 Posters 12:00-13:00 (lunch)	Afternoon Session 13:00-16:00 Oral presentations 14:30-15:00 (coffee break)