Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
MOS-AK/ESSERC Workshop in Bruges (B)
September 9, 2024
Open Directory
MOS-AK: Enabling Compact Modeling R&D Exchange
Important Date:
  • Call for Papers : Jan 2024
  • 2nd Announcement - May 2024
  • Final Workshop Program - July 2024
  • MOS-AK/ESSERC Workshop -  Sept. 9, 2024
Online Registration to be open (Aug. 2024)

 Synopsis and Workshop Topics
  • HiTech forum to discuss the frontiers of electron device modeling with emphasis on simulation-aware compact/SPICE models and its Verilog-A standardization.
  • MOS-AK Meetings are organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/Spice modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development, implementation, deployment and standardization within the main theme - frontiers of the compact modeling for nm-scale MEMS/NEMS designs, CMOS/SOI and HEMT IC simulation.
  • The specific workshop goal will be to classify the most important directions for the future development of the electron device models, not limiting the discussion to compact models, but including physical, analytical and numerical models, to clearly identify areas that need further research and possible contact points between the different modeling domains. This workshop is designed for device process engineers (CMOS, SOI, BiCMOS, SiGe, GaN, InP) who are interested in device modeling; ICs designers (RF/Analog/Mixed-Signal/SoC/Bio/Med) and those starting in that area as well as device characterization, modeling and parameter extraction engineers. The content will be beneficial for anyone who needs to learn what is really behind the IC simulation in modern device models in particular using free open source PDKs.
Speakerstentative list:
  • Dr. Rene Scholz, IHP (D), The IHP OpenPDK Initiative
  • Dr. Sebastien Martinie, CEA-Leti (F), Overview and latest updates of PSP and L-UTSOI standard model
  • Prof. Matthias Bucher, TU Crete (GR), A review of charge-based MOS Transistor modeling -- an engineering and educational tool
  • Prof. Mike Brinson, LondonMET (UK), QUCS-S - a central tool in the openPDK IC design flow
  • Dr. Jan Taro Svejda,Uni. Duisburg-Essen (D), openEMS as a versatile tool in the framework of mm-wave openPDK-based RF chip design
  • Dr. Christoph Sandner, Infineon (A); Value and Opportunities in Open-Source for Circuit Design
  • Prof. Harald Pretl, JKU (A); Designing Analog/RF Chips Using Open PDKs and Open-Source Tools
  • Dr. Frank K. Gurkaynak, ETHZ (CH); Are open source digital design flows ready for mainstream?
International MOS-AK Compact Modeling Committee

IEEE Membership
International R&D Advisory Board

Larry Nagel, Omega Enterprises Consulting (USA)
Fellow Member
Andrei Vladimirescu, UCB (USA); ISEP (FR)
Fellow Member
MOS-AK Compact Modeling TPC Chair

Wladek Grabinski, MOS-AK (EU)
Senior Member
North America TPC:  
Pekka Ojala, Exar (USA)
Geoffrey Coram, Analog Devices (USA) Senior Member
Jamal Deen, U.McMaster (CAN)
Fellow Member
Roberto Tinti, Keysight EEsof Division (USA)


South America TPC:

Gilson I Wirth, UFRGS (BR)
Senior Memner
Sergio Bampi, UFRGS (BR)
Antonio Cerdeira Altuzarra, Cinvestav-IPN (MX)
Senior Member
Roberto S. Murphy, INAOE (MX) Senior Member
Europe TPC:
Ehrenfried Seebacher, ams AG (A) .
Thomas Gneiting, AdMOS (D)
Benjamin Iniguez, URV (SP) Fellow Member
Daniel Tomaszewski, IMiF Warsaw (PL) Senior Member
Asia/Pacific TPC:
Sadayuki Yoshitomi, Kioxia (J) Member
Rakesh Vaid, University of Jammu (IN)Senior Member
Min Zhang, XMOD, Shanghai (CN)
Yuehang Xu, UESTC Chengdu (CN)

Kaikai Xu, UESTC Chengdu (CN)Senior Member
update: may.2024  (rev. c)
Contents subject to change (C)1999-2024 All rights reserved. WG