Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
Spring MOS-AK Workshop at DATE
Lausanne, March 31, 2017
Calendar
Open Directory
Books
Mission
Committee
MOS-AK: Enabling Compact Modeling R&D Exchange
Technical MOS-AK Program Promoters
IEEE Switzerland
Swiss Section: Lead Sponsor
WiE
WIE Switzerland
NEEDS
powered by nanoHUB.org
Eurotraining
IJHSES
Publishing Partner
2nd Announcement and Call for Papers
Important Dates:
  • Call for Papers - Dec. 2016
  • 2nd Announcement - Jan. 2016
  • Final Workshop Program - Feb. 2016
  • MOS-AK Workshop - March 31, 2017
Venue:
Swisstech Convention Centre
Quartier Nord de l'EPFL
Route Louis-Favre 2
CH-1024 Ecublens
Online:  Registration
 
Synopsis and Workshop Topics
Synopsis:
  • HiTech forum to discuss the frontiers of electron device modeling with emphasis on simulation-aware compact/SPICE models.
  • MOS-AK Meetings are organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/Spice modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development, implementation, deployment and standardization within the main theme - frontiers of the compact modeling for nm-scale MEMS designs and CMOS/SOI circuit simulation.
  • The specific workshop goal will be to classify the most important directions for the future development of the electron device models, not limiting the discussion to compact models, but including physical, analytical and numerical models, to clearly identify areas that need further research and possible contact points between the different modeling domains. This workshop is designed for device process engineers (CMOS, SOI, BiCMOS, SiGe) who are interested in device modeling; ICs designers (RF/Analog/Mixed-Signal/SoC) and those starting in that area as well as device characterization, modeling and parameter extraction engineers. The content will be beneficial for anyone who needs to learn what is really behind the IC simulation in modern device models.
Topics: to be covered include the following:
  • Advances in semiconductor technologies and processing
  • Compact Modeling (CM) of the electron devices
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • FOSS TCAD/EDA modeling and simulation
  • CM of passive, active, sensors and actuators
  • Emerging Devices, TFT CMOS and SOI-based memory cells
  • Organic, Bio/Med devices/technology modeling
  • Microwave, RF device modeling, HV/Power device modeling
  • Nanoscale CMOS devices and circuits
  • Technology R&D, DFY, DFT and IC Designs
  • Foundry/Fabless Interface Strategies
Speakers:
Tentative list (in alphabetic order with presentation topics)
  • Matthias Bucher, TUC (GR)
    The EKV3 for Advanced Analog/RF IC Applications
  • Sandro Carara, EPFL (CH)
    Bio/Nano/CMOS interfaces for Ultrasensitive Memristive Biosensors
  • Catherine Dehollain, EPFL (CH)
    Remotely Powered Sensor Networks for Medical Applications
  • James Greer, ASCENT/Tyndall (IE)
    Modelling
    Emerging CMOS Devices through ASCENT
  • Theodor Hillebrand, Uni Bremen (D)
    Unified charge-based Transistor Model including Degradation Mechanisms
  • Benjamin Iniguez, URV (SP)
    Compact Modeling of the Organic TFT Devices
  • Vadim Kuznetsov, Bauman TU Moscow (RU)
    The First Stable Release of Qucs-S and Advances in XSPICE Model Synthesis
  • Mathieu Luisier, ETHZ (CH)
    Physics-based Modeling of Nano-Devices: Requirements and Examples
  • Anurag Mangla, ams AG (A)
    Interactive Tool for Quick Calculation of Design Oriented MOSFET Parameters
  • Heinz-Olaf Müller, Plastic Logic (D)
    Verilog-A Model for Ferroelectrics in Organic Electronics
  • Maria-Alexandara Paun, EPFL (CH)
    Optimal Geometry Selection for Hall Sensors Integrated in CMOS Technological Process
  • Andrej Rumiantsev MPI Corp. (TW)
    New Approach to Reduce Time-to-data when Characterizing Advanced Semiconductor Devices
  • Felix Salfelder, Uni Leeds (UK)
    Semiconductor Device Compact Modelling with Ageing Effects

Extended MOS-AK Committee:
Committee
  • Local MOS-AK Organization Chair
    • Jean-Michel Sallese, EPFL (CH)
  • MOS-AK Workshop Manager
    • Wladek Grabinski, MOS-AK (EU)
  • International MOS-AK Board of R&D Advisers
    • Larry Nagel, Omega Enterprises Consulting (USA)
    • Andrei Vladimirescu, UCB (USA); ISEP (FR)
  • Technical Program Committee
    MOS-AK North America
  • Chair: Pekka Ojala, Exar Corporation
  • Co-Chair: Geoffrey Coram, Analog Devices
  • Co-Chair: Prof. Jamal Deen, U.McMaster
  • Co-Chair: Roberto Tinti, Keysight EEsof Division
    MOS-AK South America
  • Chair: Prof. Gilson I Wirth; UFRGS; Brazil
  • Co-Chair: Prof. Carlos Galup-Montoro, UFSC; Brazil
  • Co-Chair: Sergio Bampi, UFRGS, Brazil
  • Co-Chair: Antonio Cerdeira Altuzarra, Cinvestav - IPN, Mexico
    MOS-AK Europe
  • Chair: Ehrenfried Seebacher, AMS, Austria
  • Co-Chair: Alexander Petr, XFab, Germany
  • Co-Chair: Prof. Benjamin Iniguez, URV, Spain
  • Co-Chair: Franz Sischka, SisConsult, Germany
    MOS-AK Asia/South Pacific

  • Chair: Sadayuki Yoshitomi, Toshiba (J)
  • Co-Chair: Min Zhang, XMOD Technologies, (CN)
  • Co-Chair: Xing Zhou, NTU Singapore (SG)  
  • Co-Chair: A.B. Bhattacharyya, JIIT New Delhi (IN)
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No.#1093
update: Feb. 2017 (rev. d)
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